Voltage Divider Test Circuit for DRAM Leakage Compensation
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Solution Overview
Problem
In dynamic random access memories (DRAMs) like LPDDR4 and LPDDR5, the accuracy of read-out voltage at output terminals is compromised due to leakage currents, especially when ODT pads are absent, affecting the reliability of chip tests.
Innovation Solution
A voltage output test circuit is designed with a first and second voltage divider unit connected to a test power supply and ground respectively, and a third voltage divider unit that adjusts resistance between the output terminal and ground, reducing the impact of leakage currents on read-out voltage accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage signal is read out by DQ pad in LPDDR5 DRAM, then bidirectional data transmission capability is achieved, but voltage read-out accuracy deteriorates due to leakage currents
Solution Approach 1:
The test circuit is divided into multiple independent voltage divider units (first, second, and third voltage divider units), each with specific resistance values. These units can be selectively connected to the output terminal through switch units, allowing the system to segment the measurement function into manageable parts that can be optimized for different measurement conditions.
Solution Approach 2:
The circuit employs multiple voltage divider units with different resistance values (R1, R2, R3, R4) that can be selectively connected based on the expected leakage current level. By changing the resistance parameters of the connected voltage divider unit, the circuit adapts to different leakage conditions and maintains accurate voltage measurement. The switch units enable dynamic parameter selection to compensate for leakage effects.
2Reliability
If ODT pad is used to read out voltage signal, then signal integrity is improved by preventing signal reflection, but the solution is not available in LPDDR5 DRAM
Solution Approach 1:
The voltage divider units act as intermediary circuits between the output terminal and the measurement point. By introducing these resistive dividers, the circuit creates a buffered measurement path that reduces the impact of leakage currents while maintaining voltage measurement capability. This intermediary approach allows accurate measurement without requiring ODT pad functionality.
Solution Approach 2:
The test circuit incorporates switch units that can be controlled based on measured conditions to selectively connect different voltage divider units. This feedback mechanism allows the system to adapt its measurement configuration based on the actual operating conditions, ensuring accurate voltage reading regardless of leakage current levels.
3Measurement precision
If leakage current compensation is implemented by adding voltage divider units, then voltage read-out accuracy is improved, but device complexity increases
Solution Approach 1:
Multiple voltage divider units are merged into a single test circuit architecture that shares common components such as the output terminal connection, ground reference, and control logic. The switch units enable these separate divider units to be selectively combined based on measurement needs, reducing overall complexity compared to having all units permanently connected.
Solution Approach 2:
The voltage divider units serve multiple functions: they provide voltage division for measurement, act as current limiting elements, and enable adaptation to different leakage conditions. The same basic voltage divider structure (resistors connected between output terminal and ground) is reused multiple times with different resistance values, reducing design complexity through functional repetition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit improves the accuracy of read-out voltage at output terminals by adjusting the drive current based on leakage current levels, ensuring the voltage remains within a tolerable error range and enhancing the reliability of chip tests.
Implementation Method 1
a first voltage divider unit, including a first terminal and a second terminal, where the first terminal of the first voltage divider unit is electrically connected to a test power supply, and the second terminal of the first voltage divider unit is electrically connected to an output terminal
Data Source
AI summary
Embodiments of this invention provide a voltage output test circuit, a voltage divider output circuit, and a memory. The voltage output test circuit includes: a first voltage divider unit, including a first terminal and a second terminal, where the first terminal of the first voltage divider unit is connected to a test power supply, and the second terminal of the first voltage divider unit is connected to an output terminal; a second voltage divider unit, including a first terminal and a second terminal, where the first terminal of the second voltage divider unit is connected to a ground, and the second terminal of the second voltage divider unit is electrically connected to the output terminal; and a third voltage divider unit, configured to adjust a resistance between the output terminal and the ground.