Voltage-Division Driver Circuit for Adjustable Drive Signal Levels
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Solution Overview
Problem
Dedicated driver chips face challenges in meeting varying drive voltage requirements across different application scenarios, leading to high design difficulty and cost due to the need for frequent redesign and remanufacturing.
Innovation Solution
A circuit structure comprising a first and second voltage division branch, where the branches receive different power signals, allowing for adjustable output signals through pulse level stages, enabling synchronization and flexible design of output levels without changing the drive timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated driver chip is designed for specific driving requirements, then the driving performance is optimized, but the design difficulty and cost increase when application scenarios change
Solution Approach 1:
The driver chip is designed with multiple voltage division branches (first voltage division branch with first and second power signals, second voltage division branch with third and fourth power signals) that can be selectively activated through control terminals. This allows a single chip to provide multiple different drive signal amplitudes and waveforms, making it universally applicable to different electronic device driving requirements without redesign.
Solution Approach 2:
The circuit structure uses dynamic control through initial signals (first initial signal V0 with first pulse level stage and second pulse level stage) that dynamically select which voltage division branch operates. The control terminals respond to changing conditions by activating appropriate branches, enabling the driver chip to adapt its output characteristics in real-time based on application requirements.
2Adaptability or versatility
If a dedicated driver chip is redesigned for different drive voltage requirements, then the drive voltage requirement is met, but the manufacturing cost and time increase
Solution Approach 1:
The driver chip is segmented into multiple independent voltage division branches, each capable of providing specific voltage levels. The first voltage division branch handles first and second power signals, while the second voltage division branch handles third and fourth power signals. This segmentation allows selective activation of branches based on required drive voltage, eliminating the need for complete chip redesign.
Solution Approach 2:
The circuit structure changes operational parameters by selecting different power signal combinations (V1>V2, V3>V4) and using control terminals to switch between operating modes. This parameter-based adaptability allows the same hardware to meet different drive voltage requirements without physical redesign or remanufacturing.
3Adaptability or versatility
If the drive voltage is reduced to meet low voltage requirements, then the application requirement is satisfied, but the dedicated driver chip must be redesigned
Solution Approach 1:
The driver chip is designed in advance with multiple voltage division branches that can provide different voltage levels. By preparing these alternative pathways beforehand, the chip can accommodate future low voltage requirements or other voltage changes without needing redesign, thus cushioning against manufacturing costs.
Solution Approach 2:
The control terminals act as intermediaries between the input signals and the voltage division branches. They mediate the selection of appropriate voltage levels by activating specific branches based on requirements, enabling flexible voltage adaptation without direct hardware changes.
Data Source
AI summary
Provided circuit structure includes a first voltage division branch and a second voltage division branch. The first voltage division branch includes a first control terminal and a first voltage division output terminal, and the second voltage division branch includes a second control terminal and a second voltage division output terminal. The first control terminal of the first voltage division branch receives a first initial signal V0, and the first voltage division output terminal is electrically connected to the second control terminal of the second voltage division branch. At a first pulse level stage, the second voltage division output terminal outputs a first output level signal, and at a second pulse level stage, the second voltage division output terminal outputs a second output level signal different from the first output level signal.