Voltage Droop Detection Circuit for Dynamic Clock Mitigation
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Solution Overview
Problem
Modern integrated circuits face challenges in maintaining stable power supply due to rapid changes in processor core activity, leading to voltage droops that can cause timing failures and reduce performance.
Innovation Solution
A circuit is designed to detect voltage droops by using two signal delay lines with different threshold voltages, a phase detector, a reset circuit, and a clock controller. The delay lines are calibrated to have equal delays at a target voltage, allowing the circuit to adjust the clock frequency based on the comparison of the delayed signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the power supply provides rapid power increase to meet processor core activity changes, then the power demand is satisfied, but voltage droop occurs due to physical limitations
Solution Approach 1:
The delay lines are pre-configured with different threshold voltages to predict and detect voltage droop conditions before they cause timing failures. The circuit proactively monitors voltage stability by comparing delayed signals that represent different voltage thresholds, allowing the system to take preventive action by adjusting clock frequency before actual timing failures occur.
2Reliability
If the clock frequency is lowered to mitigate voltage droop, then voltage stability is maintained, but performance is reduced
Solution Approach 1:
The clock frequency is dynamically adjusted based on real-time voltage conditions detected by the delay lines and phase detector. Instead of using a fixed conservative frequency, the system continuously monitors voltage stability through the comparison of delayed signals and adapts the clock frequency accordingly, allowing the processor to operate at higher frequencies when voltage is stable and reduce frequency only when necessary to prevent timing failures.
3Measurement precision
If delay lines with different threshold voltages are used to detect voltage droop, then detection precision is improved, but device complexity increases
Solution Approach 1:
The voltage detection function is segmented into multiple parallel delay lines, each with a different threshold voltage. This segmentation allows the circuit to detect different voltage droop thresholds simultaneously by comparing the output times of the delayed signals from each line, providing precise multi-level voltage monitoring without requiring a single complex detection mechanism.
Data Source
AI summary
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal. A second delay line outputs a second delayed signal. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.