Voltage Droop Detection Using Delay Element Chains
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Solution Overview
Problem
During chip operation, sudden increases in activity can lead to voltage droop due to inductance, causing current to lag and resulting in functional failures, as conventional systems struggle to maintain stable voltage while varying power requirements.
Innovation Solution
A system that detects voltage droop events by analyzing the number of delay elements a clock signal travels through, and compensates by modifying the clocking signal frequency without reconfiguring the phase locked loop, using a controller and programmable delay elements to form a modified clocking signal that reduces frequency flexibly and quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the base voltage is increased to prevent functional failure during voltage droop, then the chip reliability is improved, but the power requirement increases
Solution Approach 1:
The system dynamically changes the clocking signal frequency parameter in response to detected voltage droop events. By reducing the clock frequency, the dynamic power consumption (which is proportional to frequency) decreases, allowing the chip to operate reliably during voltage droop without requiring increased base voltage
Solution Approach 2:
The system employs feedback by continuously monitoring the clock signal propagation through delay elements to detect voltage droop events. Based on this feedback, the controller dynamically adjusts the clocking signal frequency to prevent functional failures, achieving reliability improvement without increasing power requirements
2Reliability
If the frequency of the clocking signal is reduced to compensate for voltage droop, then the chip functionality is maintained, but the performance drops significantly
Solution Approach 1:
The system dynamically adjusts the clocking signal frequency based on real-time detection of voltage droop events. The frequency is reduced only when and where needed (during droop events in specific clock domains) rather than globally and continuously, maintaining performance in unaffected areas while ensuring functionality in affected areas
Solution Approach 2:
The voltage droop detection and compensation is applied locally to specific clock domains and time periods where droop events occur. The system identifies which clock signals are affected and adjusts only those, leaving other clock signals at full frequency to maintain overall chip performance
3Reliability
If the phase locked loop is reconfigured to output a lower frequency to compensate for droop, then the voltage droop is compensated, but the response time is too slow (microseconds range)
Solution Approach 1:
The system extracts the voltage droop detection function from the phase locked loop and implements it separately using delay elements and edge transition detectors. This allows droop detection and compensation to occur independently and much faster than PLL reconfiguration, achieving rapid response without the microseconds delay of PLL reconfiguration
4Measurement precision
If more delay elements are used to detect droop events accurately, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The system uses a sufficient but not excessive number of delay elements to achieve adequate droop detection precision. By detecting edge transitions through a chain of delay elements, the system achieves reliable droop detection with a practical number of components, avoiding unnecessary complexity while maintaining sufficient measurement precision
Data Source
AI summary
A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.