Predictive Voltage Droop Management via Stall Event Throttling

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Solution Overview

Problem

Modern multicore processing devices face voltage droop issues due to varying processing loads, leading to microarchitectural stall events and potential core shutdowns, as existing voltage sensing mechanisms often fail to prevent significant voltage drops in time.

Innovation Solution

A predictive voltage droop management system is embedded within memory devices, which determines stall events, timing margins, and impending voltage droops in real-time, integrating this data to proactively initiate throttle actions on processor cores through core throttling circuits, thereby preventing voltage droop and microarchitectural stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If voltage sensing mechanisms are used to detect voltage drops, then voltage monitoring capability is improved, but the response time is insufficient to prevent significant voltage drops

Engineering Contradiction:
Improvevoltage monitoring capabilityVSAvoidresponse time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary actions by detecting stall events and calculating timing margins before voltage droop occurs. The predictive voltage droop management system identifies impending stall events and proactively initiates throttle actions to prevent voltage droop, rather than merely reacting after voltage drops are detected.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system applies beforehand cushioning by using timing margin calculations to create a safety buffer before voltage droop occurs. The timing margin represents a predictive buffer that allows the system to take preventive throttle actions before the voltage droop becomes significant, cushioning against the harmful effect of voltage drops.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If processing loads on cores are increased to improve productivity, then productivity is improved, but voltage droop occurs leading to microarchitectural stall events

Engineering Contradiction:
Improveprocessing throughputVSAvoidvoltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system implements feedback by continuously monitoring stall events and timing margins, and using this information to dynamically adjust throttle actions. The predictive voltage droop management system creates a closed-loop control mechanism where the detection of stall events and calculation of timing margins feed back into the throttle control decisions to maintain voltage stability while allowing high processing loads.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system applies dynamics by making the throttle control adaptive and dynamic rather than static. The throttle actions are dynamically adjusted based on real-time detection of stall events and continuous calculation of timing margins, allowing the system to optimize between productivity and voltage stability under varying processing conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11586265B2Voltage droop management through microarchitectural stall events
Publication Date: 2023.02.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11586265B2 patent drawing
  • US11586265B2 patent drawing
  • US11586265B2 patent drawing

AI summary

Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.