Voltage Droop Monitor Using TDC and Delay-Line Phase Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing voltage droop monitoring (VDM) systems face challenges in achieving sufficient voltage resolution, response time, and area scaling, particularly due to limitations in voltage-controlled oscillators (VCO) and analog-digital converters (ADC), which restrict their placement and efficiency in advanced process nodes.
Innovation Solution
A VDM system utilizing a reference digitally-controlled delay line (DCDL), phase interpolators (PI), and time-to-digital converters (TDC) to generate a TDC code combination that varies with voltage variations, replacing the need for reference voltage and allowing for scalable resolution and sampling rate, while using a calibration circuit to adjust delay parameters for precise monitoring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If VCO type of VDM is used to monitor voltage regulator, then voltage sensing capability is achieved, but latency is increased due to counter accumulation requirements
Solution Approach 1:
The patent replaces the mechanical counter accumulation system with a time-to-digital converter (TDC) that directly measures time intervals. Instead of using a voltage-controlled oscillator that requires counter accumulation to achieve voltage measurement, the invention uses a delay-locked loop (DLL) and TDC to directly convert time delay information into digital voltage readings, thereby eliminating the latency associated with counter accumulation while maintaining voltage sensing capability.
2Measurement precision
If finer voltage resolution is achieved in VCO type VDM, then measurement precision is improved, but sampling rate must be reduced to compensate
Solution Approach 1:
The patent changes the fundamental measurement parameter from frequency-based (VCO) to time-based (TDC). By using a time-to-digital converter that directly measures time delays through delay elements, the system achieves fine voltage resolution without the trade-off of reduced sampling rate. The time delay measurements can be performed at high speeds, enabling both high resolution and high sampling rate simultaneously.
3Measurement precision
If ADC type of VDM is used to compare voltage difference, then voltage monitoring is achieved, but resolution and sampling rate are limited by analog-digital converter constraints
Solution Approach 1:
The patent replaces the analog-to-digital converter approach with a time-to-digital conversion system. Instead of using an ADC to directly convert voltage differences to digital codes, the invention uses a delay-locked loop and time-to-digital converter to measure time delays that are proportional to voltage differences. This substitution eliminates the resolution and sampling rate limitations inherent in ADC technology while simplifying the overall system architecture.
4Measurement precision
If reference voltage generation is implemented in VDM, then voltage comparison capability is achieved, but placement difficulty increases
Solution Approach 1:
The patent extracts and eliminates the reference voltage generation requirement from the voltage droop monitor system. By using a delay-locked loop and time-to-digital converter that operates with a single voltage supply, the invention removes the need for additional reference voltage sources. This extraction of the reference voltage requirement significantly simplifies placement and integration, allowing the VDM to be easily incorporated into existing circuits without additional voltage source infrastructure.
Data Source
AI summary
The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method. The method includes: receiving a first reference clock signal and delaying the first reference clock signal as a first clock signal; delaying the first clock signal as a corresponding second clock signal; receiving the corresponding second clock signal from the corresponding first DCDL and generating a corresponding third clock signal via modifying a phase of the corresponding second clock signal; receiving the corresponding third clock signal; receiving a second reference clock signal; and collectively outputting a TDC code combination based on the second reference clock signal and the corresponding third clock signal, wherein the TDC code combination varies in response to a voltage variation of a to-be-monitored voltage.