Vertical Nanowire FET Power Switch Cell Layout
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face increased power consumption due to excessive scaling, leading to high off-current and power supply voltage drops, with no prior art documenting a layout structure for power switch cells using vertical nanowire FETs.
Innovation Solution
A layout structure for a power switch cell utilizing vertical nanowire FETs, where the top electrode of the VNW FET is connected to the global power interconnect, reducing resistance and preventing power supply voltage drops, while maintaining a small area footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are scaled down, then integration degree and operating speed are improved, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from conventional planar transistors to vertical nanowire FETs, changing the transistor architecture from two-dimensional planar structure to three-dimensional vertical structure. This dimensional change enables better current control through the nanowire channel while maintaining scaling benefits, thereby reducing off-current and power consumption despite high integration density
2Area of stationary object
If power switch area is reduced, then area efficiency is improved, but power supply voltage drop increases
Solution Approach 1:
The patent employs vertical nanowire FETs with three-dimensional structure to achieve high drive capability in a compact footprint. The vertical channel provides excellent current control and low on-resistance, enabling the power switch to maintain low voltage drop while occupying minimal area. The top electrode configuration optimizes the current path to further reduce resistance
Solution Approach 2:
The patent utilizes the unique electrical parameters of vertical nanowire FETs, including high drive capability and low on-resistance, to achieve effective power switching in a compact area. The parameter optimization of the VNW FET structure enables simultaneous achievement of small area and low voltage drop
Data Source
AI summary
A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.