Voltage-Enhanced Feedback Sense Amplifier for Resistive Memory
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Solution Overview
Problem
In long bit-line length resistive memory arrays, the slow accumulation of voltage difference between bit-line and reference voltages leads to increased developing time, resulting in read failures and low sensing yield due to small voltage differences, especially when resistance values are low, affecting sensing speed and efficiency.
Innovation Solution
A voltage-enhanced-feedback sense amplifier is introduced, comprising a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier with high-gain modules that cross-couple to suppress voltage drops across bit lines, enhancing the sensing margin and amplifying voltage levels to improve sensing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit line length is increased to achieve high density memory array, then the memory density is improved, but the developing time is increased and sensing yield is reduced due to slow voltage difference accumulation
Solution Approach 1:
A pre-amplifier stage is introduced as an intermediary between the bit lines and the main sense amplifier. This pre-amplifier (comprising transistors M1-M4 and capacitors C1-C2) initially amplifies the small voltage difference on the bit lines before it is fed to the main sense amplifier, thereby accelerating the voltage accumulation process and reducing the developing time penalty associated with long bit lines
Solution Approach 2:
The patent implements a feedback mechanism where the output of the sense amplifier is fed back to the pre-amplifier through transistors M5-M8. This feedback loop continuously reinforces the voltage difference signal, enabling faster voltage accumulation and reducing the sensing time for long bit line configurations
2Speed
If the resistance value of resistive memory is decreased to improve write speed, then the write speed is improved, but the voltage difference between bit lines drops quickly causing low sensing yield
Solution Approach 1:
The pre-amplifier performs preliminary amplification of the voltage difference signal immediately after it is generated on the bit lines. By having this initial amplification stage in place before the main sensing operation, the system can handle the quickly dropping voltage signals that result from low-resistance memory cells, thereby maintaining high sensing yield despite fast write speeds
3Device complexity
If conventional sense amplifier is used without pre-amplification, then the device complexity is reduced, but the sensing margin is insufficient leading to read failures
Solution Approach 1:
The sensing operation is segmented into two distinct stages: a pre-amplification stage (M1-M4, C1-C2) that initially boosts the small voltage difference, and a main amplification stage (M5-M8 and subsequent sense amplifier) that provides the final output. This segmentation allows each stage to be optimized for its specific function, achieving high sensing margin while maintaining reasonable device complexity
Data Source
AI summary
A voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. A first bit-line amplifying module receives a voltage level of the second input node to suppress a voltage drop of the first bit line and amplifies a voltage level of the first input node according to a voltage level of the first bit line. A second bit-line amplifying module receives the voltage level of the first input node to suppress a voltage drop of the second bit line and amplifies the voltage level of the second input node according to a voltage level of the second bit line. A margin enhanced voltage difference is greater than a read voltage difference.