Automated Voltage Data Extraction for Semiconductor Layout Verification
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Solution Overview
Problem
The increasing complexity of semiconductor devices poses challenges in accurately and efficiently performing voltage-dependent design rule checks (VDRCs), particularly due to the risk of human error in manually entering voltage data, which can lead to inaccuracies and increased complexity.
Innovation Solution
Incorporating voltage data based on simulations into the semiconductor device layout using tools like location data extraction, voltage data extraction, and voltage marker generation, enabling automated and accurate VDRCs with improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If manual entry of voltage data is used for VDRC, then ease of operation is improved, but measurement precision deteriorates due to human error
Solution Approach 1:
The system performs self-service by automatically extracting voltage data from simulation results and incorporating it into the layout without requiring manual human intervention. The automated voltage data extraction tool reads simulation results and the voltage marker generation tool automatically places voltage markers in the layout, eliminating human error while maintaining operational simplicity through automation.
Solution Approach 2:
The patent replaces the mechanical manual data entry process with an automated computer-based system. The voltage data extraction tool and voltage marker generation tool use computational algorithms to automatically retrieve and process voltage information from simulation results, substituting human manual operations with automated digital processing to eliminate errors.
2Measurement precision
If automated voltage data extraction is implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The system segments the complex VDRC process into distinct functional modules: a voltage data extraction tool that reads simulation results, a voltage marker generation tool that processes and places markers in the layout, and a VDRC tool that performs the actual verification. This segmentation breaks down the complex automated system into manageable, independent components that can be developed and maintained separately.
Solution Approach 2:
The patent introduces intermediary tools between the simulation results and the VDRC process. The voltage data extraction tool acts as an intermediary that reads simulation data, and the voltage marker generation tool acts as an intermediary that translates this data into layout markers. These intermediary components simplify the overall system architecture by creating clear data transformation stages.
3Productivity
If comprehensive chip coverage is achieved through automated VDRC, then productivity is improved, but device complexity increases
Solution Approach 1:
The automated VDRC system provides universal applicability across the entire semiconductor device layout. The voltage marker generation tool can process any layout file, and the VDRC tool can verify any design against the extracted voltage data, making the system universally applicable to different device types and design stages without requiring custom procedures for each case.
Solution Approach 2:
The system enables continuous automated verification throughout the design process. The voltage data is extracted from simulation results and immediately incorporated into the layout for VDRC, creating a continuous feedback loop that eliminates gaps between simulation and verification. This continuous action improves productivity by eliminating manual intervention steps and rework.
Data Source
AI summary
In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.