Voltage Follower Circuit with Dynamic Current Paths

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Solution Overview

Problem

Conventional voltage follower circuits face challenges in maintaining a stable output voltage when load current fluctuates, as the slew rate decreases with increased load, requiring high current supply to the differential amplifier, which is inefficient.

Innovation Solution

The voltage follower circuit employs a differential MOS transistor circuit with nMOS and pMOS transistors, current mirror circuits, and an output buffer to actively amplify differential currents, ensuring the output voltage remains constant by adjusting the gate voltage based on load current, thereby maintaining a high slew rate without increasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the slew rate is increased to maintain stable output voltage during load current fluctuation, then the output voltage stability is improved, but the power consumption increases due to high current supply to the differential amplifier

Engineering Contradiction:
Improveoutput voltage stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic current allocation by switching between a first current path (for normal operation) and a second current path (for transient response). The circuit dynamically adjusts the operating current of the differential amplifier based on whether a voltage difference exists between input and output terminals, enabling high slew rate only when needed while maintaining low power consumption during steady state.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the current parameter dynamically by introducing a second current path that provides additional current during transient conditions. The circuit monitors the voltage difference between input and output terminals and activates the second current path when needed, thereby changing the operating current parameter from a constant low value to a higher value during transients, achieving high slew rate without continuous high power consumption.

Inventive Principle:
Principle #35Parameter changes

2Power

If a large load is driven, then the output capability is improved, but the slew rate decreases because the gate capacity of the output buffer increases

Engineering Contradiction:
Improveoutput capabilityVSAvoidslew rate
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The patent dynamically adjusts the current supplied to the differential amplifier based on the operating conditions. When a large load is driven, the circuit detects the increased demand and activates the second current path to provide additional current, thereby maintaining high slew rate despite the increased gate capacity of the output buffer. This dynamic current adjustment allows the circuit to adapt to varying load conditions.

Inventive Principle:
Principle #15Dynamics

3Power

If the gate capacity of the output buffer is increased to drive large loads, then the output capability is improved, but the slew rate decreases

Engineering Contradiction:
Improveoutput capabilityVSAvoidslew rate
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The patent changes the current parameter dynamically by introducing a second current path that provides additional current during transient conditions. When large loads are driven and the gate capacity increases, the circuit detects the condition and activates the second current path, thereby changing the operating current from a standard value to a higher value, which compensates for the reduced slew rate caused by increased gate capacity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10873305B2Voltage follower circuit
Publication Date: 2020.12.22 KK TOSHIBA
  • US10873305B2 patent drawing
  • US10873305B2 patent drawing
  • US10873305B2 patent drawing

AI summary

A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor.