Hardware Voltage-Frequency Scheduler for Multithreaded Microprocessors
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Solution Overview
Problem
Current dynamic voltage scaling (DVS) techniques in multithreaded microprocessors have limited granularity due to software implementations, which are slow to adapt to fine-grained voltage-frequency changes, leading to suboptimal energy savings and increased processor bandwidth usage.
Innovation Solution
A hardware-based fine-grained voltage-frequency scheduler that operates concurrently with thread and execution units, calculating aggregate utilization across threads to adjust voltage and frequency within a small number of clock cycles, allowing for aggressive scaling based on application-specified quality-of-service requirements and instruction completion information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based dynamic voltage scaling is used, then implementation simplicity is maintained, but adaptation speed to fine-grained voltage-frequency changes is slow
Solution Approach 1:
The patent replaces software-based voltage-frequency scheduling with a hardware-based scheduler that operates independently of the instruction pipeline. This hardware scheduler uses dedicated circuitry to monitor processor utilization and control voltage-frequency changes, eliminating the latency inherent in software implementations while maintaining simplicity through dedicated hardware logic rather than complex software algorithms.
Solution Approach 2:
The patent introduces an intermediary hardware voltage-frequency scheduler that acts as a mediator between the processor's execution units and the power supply system. This intermediary component independently monitors utilization metrics and coordinates voltage-frequency adjustments, allowing the main instruction pipeline to continue executing without interruption while the scheduler handles the complexity of power management.
2Use of energy by moving object
If fine-grained voltage-frequency scaling is implemented, then energy savings are maximized, but processor bandwidth for instruction execution is consumed
Solution Approach 1:
The patent segments the processor into two independent functional components: the instruction execution pipeline and the voltage-frequency scheduler. The scheduler operates as a separate entity that monitors aggregate processor utilization across multiple threads and coordinates voltage-frequency changes independently of instruction execution. This segmentation allows fine-grained power management without consuming instruction bandwidth, as the scheduler uses dedicated utilization monitoring circuits rather than processing instruction cycles.
Solution Approach 2:
The hardware voltage-frequency scheduler operates continuously in the background, monitoring processor utilization and preparing voltage-frequency adjustments without interrupting the instruction execution pipeline. The scheduler maintains continuous oversight of aggregate utilization metrics and can rapidly respond to changes in processor demand, ensuring that voltage-frequency scaling occurs smoothly without impacting ongoing instruction execution or requiring bandwidth consumption.
3Productivity
If multiple thread contexts are maintained for concurrent execution, then thread switching performance is improved, but resource consumption and complexity increase
Solution Approach 1:
The patent merges the voltage-frequency scheduling function with the existing thread context management infrastructure. The hardware scheduler aggregates utilization information from multiple thread contexts and makes unified voltage-frequency decisions based on the collective state of all threads. This merging approach allows the system to maintain multiple thread contexts for concurrent execution while using a single centralized scheduling mechanism to manage power consumption, avoiding the need for separate per-thread power management complexity.
Data Source
AI summary
A multithreaded microprocessor includes a thread scheduler and voltage-frequency scheduler (VFS). The thread scheduler uses application-specified QoS requirements, which include required instruction completion rates, and instruction completion information from execution units to schedule the priorities of the threads at which the thread scheduler issues instructions to the execution units. Concurrently, the VFS uses the instruction completion and QoS information to calculate an aggregate utilization of the microprocessor by all the active threads when it is time to scale the voltage-frequency. The aggregate utilization is an effective measure of the amount of work left to be performed relative to the rate requirements. The VFS scales the voltage-frequency based on the aggregate utilization.