DRAM Voltage Generation Circuit Background Calibration

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Solution Overview

Problem

Unstable bit line pre-charge voltage in DRAM leads to reduced sensing margin and performance deterioration due to dead zones in the bit line pre-charge voltage distribution, causing sensing errors.

Innovation Solution

A voltage generation circuit with an offset compensator, comparator, and background calibration circuit that generates a bit line pre-charge voltage without dead zones by controlling the target short current through the driver, ensuring uniform output and minimizing voltage distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a bit line pre-charge voltage is generated without background calibration, then the device complexity is reduced, but the voltage stability deteriorates and dead zones appear in the voltage distribution

Engineering Contradiction:

Improvevoltage generation circuit complexityVSAvoidbit line pre-charge voltage stability

Core Design Contradiction:

Device complexityVSStability of the object's composition

Solution Approach 1:

The background calibration circuit performs preliminary calibration of the driver before normal operation to establish accurate offset codes. This preliminary action ensures that the driver outputs the correct bit line pre-charge voltage without dead zones, resolving the voltage stability issue while maintaining acceptable device complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The calibration circuit uses feedback mechanisms to monitor the driver output and adjust the offset code accordingly. By comparing the actual bit line pre-charge voltage with the target voltage, the system dynamically corrects deviations and eliminates dead zones, achieving stable voltage output.

Inventive Principle:

Principle #23Feedback

2Ease of operation

If the offset code is not calibrated, then the ease of operation is improved, but the sensing margin is reduced due to unstable bit line pre-charge voltage

Engineering Contradiction:

Improvevoltage generation operation simplicityVSAvoidsensing margin

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The calibration circuit operates automatically during background calibration without requiring external intervention. The system self-adjusts the offset code to eliminate dead zones, ensuring reliable sensing margin while maintaining ease of operation through automated calibration.

Inventive Principle:

Principle #25Self-service

3Measurement precision

If background calibration is performed to eliminate dead zones, then the sensing accuracy is improved, but the device complexity increases due to additional calibration circuits

Engineering Contradiction:

Improvedata sensing accuracyVSAvoidvoltage generation circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The calibration circuit focuses specifically on calibrating the offset code for the bit line pre-charge voltage driver, applying quality improvement locally where needed rather than throughout the entire memory device. This targeted approach enhances sensing accuracy while minimizing overall device complexity.

Inventive Principle:

Principle #3Local quality

4Adaptability or versatility

If the bit line pre-charge voltage has wide distribution, then the adaptability is improved, but the sensing margin is reduced and performance deteriorates

Engineering Contradiction:

Improvevoltage distribution rangeVSAvoidsensing performance

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The calibration circuit changes the offset code parameter to shift the bit line pre-charge voltage distribution away from dead zones. By adjusting this parameter, the system maintains adequate voltage distribution range while eliminating the harmful concentration of voltages in dead zones, thereby improving sensing performance.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS10741242B2Memory devices including voltage generation circuit for performing background calibration

Publication Date: 2020.08.11 SAMSUNG ELECTRONICS CO LTD

AI summary

Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.