Voltage Isolation Pathways for Buffer Placement in Multi-Power Domain ICs
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Solution Overview
Problem
In multi-power domain integrated circuit designs, buffering signals that traverse areas with components of one power domain to reach components of a different power domain is challenging due to increased routing congestion and inefficient resource allocation, as existing methods require placing buffers within the same area as the first power domain's circuitry, leading to suboptimal signal propagation and congestion issues.
Innovation Solution
The approach involves defining pre-determined voltage pathways on a semiconductor surface to isolate and buffer signals from a second power domain, allowing buffers to be placed in reserved areas within the first power domain, thereby optimizing signal routing and reducing congestion by limiting buffer placement to specific patterned areas associated with the second power domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are placed in the same area as first power domain circuitry to buffer second power domain signals, then signal propagation is enabled across power domains, but routing congestion is significantly increased
Solution Approach 1:
The patent divides the semiconductor device into multiple isolation regions separated by voltage isolation pathways. Each isolation region can contain buffers for different power domains, segmenting the routing paths and preventing congestion in any single area while enabling signal propagation across power domain boundaries.
Solution Approach 2:
The voltage isolation pathway acts as an intermediary structure that enables signal buffering between different power domains without requiring direct placement of buffers in congested areas. The pathway provides a dedicated routing channel that mediates the interaction between first and second power domain signals.
2Device complexity
If buffers are placed in reserved areas within first power domain, then routing congestion is reduced, but signal transmission efficiency may be compromised
Solution Approach 1:
The patent introduces voltage isolation pathways as a new dimensional organizing structure for buffer placement. Instead of placing buffers only within power domain areas (2D placement), the pathways provide a third dimension (dedicated routing channels) for buffer placement, allowing efficient signal transmission while reducing congestion in original power domain areas.
3Productivity
If pre-determined voltage pathways are defined to isolate and buffer second power domain signals, then resource allocation is optimized, but layout complexity increases
Solution Approach 1:
The voltage isolation pathways are pre-determined and defined during the design phase before final buffer placement and routing. This preliminary action establishes a structured framework that simplifies subsequent resource allocation and buffer placement, even though it adds an initial layout step.
Data Source
AI summary
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.