Voltage Keeper Circuit for Memory Macro Leakage Control
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Solution Overview
Problem
In memory macros, voltage keepers face challenges in maintaining logical values due to manufacturing process variations and transistor size affecting poly pattern accuracy and memory cell efficiency, requiring multiple implementations and large die areas.
Innovation Solution
The implementation of a memory macro with a voltage keeper circuit that includes symmetrical structures and transistors to effectively manage logical values by adjusting transistor strength based on logical data stored, using NMOS and PMOS transistors to maintain high and low logical values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple voltage keepers are implemented in different sections of the memory macro to cover manufacturing process variations, then reliability is improved, but device complexity and die area increase
Solution Approach 1:
The memory macro is divided into multiple sections (first section and second section), with voltage keepers implemented in each section. This segmentation allows independent optimization of each voltage keeper while covering manufacturing process variations across different regions of the macro.
Solution Approach 2:
Each voltage keeper is designed with locally optimized transistor sizes and strengths tailored to its specific section's requirements. The first voltage keeper has transistors sized appropriately for the first section's process variations, while the second voltage keeper is optimized for the second section, allowing each to maintain reliability without requiring all sections to use the same oversized design.
2Strength
If a large transistor length is used for the voltage keeper to ensure strength, then voltage keeping capability is improved, but poly pattern accuracy of the memory array deteriorates
Solution Approach 1:
The voltage keeper uses transistors with larger lengths only in the specific regions where voltage keeping is required, while the memory array transistors maintain their standard smaller lengths for optimal poly pattern accuracy. This localized application of large transistor length prevents degradation of overall manufacturing precision while providing sufficient voltage keeping strength where needed.
Solution Approach 2:
The circuit is segmented into voltage keeper regions and memory array regions, allowing different transistor length specifications in each region. The voltage keeper transistors can have larger lengths for strength without affecting the poly pattern accuracy of the memory array transistors, as they are manufactured as distinct structures in their respective sections.
3Strength
If a large die area is allocated to the voltage keeper to ensure sufficient strength, then voltage keeping capability is improved, but memory cell efficiency deteriorates
Solution Approach 1:
The voltage keeper occupies only the specific die area required for its function in each section, with transistors sized appropriately for local requirements rather than using a uniform large size across the entire macro. This localized optimization ensures sufficient voltage keeping strength while minimizing the total die area consumed, thereby preserving memory cell efficiency.
Solution Approach 2:
The voltage keeper strength is dynamically adjusted through controlled transistor sizing in each section based on actual process variation requirements rather than using a fixed large size throughout. This dynamic optimization allows the voltage keeper to be strong enough where needed while occupying minimal die area, thus maintaining high memory cell efficiency.
Data Source
AI summary
A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.