Voltage Kick to Non-Selected Word Lines in NAND Memory
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Solution Overview
Problem
In non-volatile memory systems, particularly in NAND-type architectures, the variation in bit line and word line settling times across different blocks leads to inefficiencies in programming and reading operations, resulting in slower performance and increased power consumption due to the need to synchronize timings based on the slowest blocks, which can lead to errors and suboptimal performance.
Innovation Solution
The implementation of block segmentation and differential timing for bit lines and word lines based on their proximity to sense amplifiers, allowing for faster settling times for blocks closer to the sense amps while accommodating slower far blocks, along with the use of dummy word lines and reverse kicks to optimize voltage application and reduce settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If block segmentation and differential timing are implemented, then bit line and word line settling times are optimized and performance is enhanced, but device complexity increases due to additional control circuitry and timing management
Solution Approach 1:
The memory array is divided into multiple blocks, each with independent timing control. This segmentation allows each block to operate with optimized timing parameters specific to its characteristics, enabling faster settling times for blocks closer to sense amplifiers while accommodating slower far blocks independently, thus resolving the contradiction between performance and complexity by localizing control rather than implementing global complex timing management
Solution Approach 2:
Different timing parameters are applied to different blocks based on their local characteristics (proximity to sense amplifiers). Blocks closer to sense amplifiers use shorter settling times while farther blocks use longer times. This local quality approach optimizes performance for each block's specific conditions without requiring the entire system to operate at the speed of the slowest block, thereby improving productivity without proportionally increasing overall complexity
2Reliability
If timing is synchronized based on the slowest blocks, then all blocks can operate reliably, but performance is reduced and power consumption increases due to waiting for slow blocks
Solution Approach 1:
By segmenting the memory into independently timed blocks, each block can complete its operations at its own optimized speed. The segmentation allows fast blocks to complete operations quickly while slow blocks take their required time, with each block's reliability ensured through independent timing control rather than forcing all blocks to wait for the slowest one
Solution Approach 2:
The system transitions from static global timing synchronization to dynamic local timing control. Each block can dynamically adjust its timing parameters based on its specific characteristics and operational state. This dynamic approach allows blocks to operate at optimal speeds rather than being constrained by a fixed global timing schedule, improving productivity while maintaining reliability through adaptive control
3Ease of operation
If global timing synchronization is used, then timing management is simpler, but performance is suboptimal and power consumption is higher due to waiting for slow blocks
Solution Approach 1:
The memory system is segmented into independently controlled blocks, each with its own timing parameters. This segmentation transforms the timing management from a complex global synchronization problem into multiple simpler local timing control problems. Each block can be managed with straightforward timing control while the overall system achieves superior performance through the combined effect of optimized local timings
Solution Approach 2:
Timing parameters are pre-configured for each block based on their characteristics (such as distance from sense amplifiers). This preliminary action allows each block to operate with optimized timing from the start of the operation, eliminating the need for complex real-time global synchronization while maintaining simple local control and achieving high productivity
Data Source
AI summary
When applying a programming voltage at one end of a word line of a non-volatile memory circuit, if the word line has a large RC constant the far end of the word line will not rise as fast as the driven end, which can adversely affect device performance. To more quickly raise the voltage on the selected word line, a voltage kick is applied to non-selected word lines, such as dummy word lines, by way of a non-selected sub-block of the selected block. The channel of NAND strings in the non-selected sub-block is used to transfer the kick to the far end of the selected word line of the selected sub-block.