Voltage Level Converter Circuit Transition Time Optimization
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Solution Overview
Problem
Conventional voltage level converter circuits in semiconductor integrated circuits experience long transition times when switching from high to low levels due to the simultaneous ON state of PMOS and NMOS transistors, and reducing ON resistance does not effectively shorten this time.
Innovation Solution
A voltage level converter circuit configuration using a combination of NMOS and PMOS transistors with specific connections and power source voltages, where the mutual conductance of PMOS transistors is minimized to reduce current flow and transition time, and additional resistive elements or transistors with lower threshold values are used to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the voltage level converter circuit uses a conventional complementary circuit configuration with PMOS and NMOS transistors, then the circuit can perform voltage level conversion, but the transition time from high level to low level becomes long due to simultaneous ON state of both transistors
Solution Approach 1:
The patent segments the voltage level conversion function into separate high-level output circuit (using PMOS transistor) and low-level output circuit (using NMOS transistor), preventing simultaneous conduction. Each transistor operates in distinct phases controlled by the differential input signals, eliminating the overlap period that causes long transition times in conventional complementary circuits.
Solution Approach 2:
Instead of using the conventional approach where both PMOS and NMOS transistors are simultaneously controlled in a complementary fashion, the patent inverts the control strategy by using differential signaling that ensures when one transistor is ON, the other is OFF. The gate voltages are inverted relative to each other, preventing simultaneous conduction and reducing transition time.
2Speed
If the ON resistance of the NMOS transistor is reduced to shorten transition time, then the transistor switches faster, but the transition time from high level to low level cannot be effectively improved
Solution Approach 1:
The patent introduces an intermediate differential signaling stage that mediates between the input signal and the output transistors. This intermediate stage ensures proper timing control and prevents direct simultaneous activation of PMOS and NMOS transistors, allowing the circuit to achieve fast transition times without compromising signal integrity or requiring extreme reduction of ON resistance.
3Speed
If additional transistors are added to the voltage level converter circuit to improve performance, then the transition time is shortened, but the device complexity increases
Solution Approach 1:
The patent makes each transistor in the circuit perform multiple functions. For example, the PMOS and NMOS transistors not only perform voltage level conversion but also act as switches controlled by differential signals, and their gate structures serve as part of the differential input stage. This multi-functionality reduces the need for additional dedicated transistors for each function, minimizing circuit complexity while achieving fast transition times.
Data Source
AI summary
Differential signals are supplied to gates of first and second transistors. One end and a gate of a third transistor are connected to a signal output node. One end and a gate of a fourth transistor are connected to the other end of the second transistor. A fifth transistor is connected between a power source and the other end of the third transistor. A sixth transistor is connected between a power source and the other end of the fourth transistor. A seventh transistor is inserted between the power source and the signal output node. An eighth transistor is inserted between the power source and the common connection node of the second and fourth transistor, and a gate of the eighth transistor is connected to the gate of the sixth transistor.