Multi-Stage Voltage Level Shifter for Safe CMOS Terminal Voltages
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Solution Overview
Problem
Conventional CMOS voltage level shifter circuits face issues with transistor damage due to excessive voltage differences between terminals, particularly as nominal voltage levels decrease in advanced CMOS processes, leading to potential transistor damage from power source voltages higher than the nominal voltage.
Innovation Solution
A voltage level shifter circuit design comprising multiple control and pull-up/pull-down circuits that manage output voltages across different reference levels, ensuring that voltage differences between transistor terminals do not exceed nominal voltages by using a hierarchical structure of reference voltages (VSS, VDDH, and VDDHX2) to regulate output voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS voltage level shifter circuit is used, then voltage level shifting function is achieved, but transistor damage occurs due to excessive voltage difference between terminals
Solution Approach 1:
The voltage level shifting process is segmented into multiple stages. Instead of directly shifting from low voltage to high voltage, the circuit uses intermediate voltage levels (first intermediate voltage and second intermediate voltage) to break down the voltage transition into smaller steps, ensuring that voltage difference across any transistor terminal never exceeds the nominal voltage rating.
Solution Approach 2:
The patent introduces intermediary voltage levels and control circuits that act as mediators between the input and output voltage domains. These intermediate voltages serve as buffer zones that prevent direct exposure of transistors to excessive voltage differences, thereby protecting the transistor terminals from damage.
2Area of stationary object
If transistor size is continuously shrunk to reduce chip area, then chip area is reduced and power consumption is saved, but allowable voltage difference between terminals is reduced
Solution Approach 1:
The voltage shifting operation is divided into multiple controlled stages with intermediate voltage levels. This segmentation allows the use of smaller transistors without exposing them to excessive voltage differences, as each stage operates within safe voltage margins while collectively achieving the overall voltage level shift.
Solution Approach 2:
The circuit dynamically adjusts the voltage levels at different nodes based on the operating state. Control circuits dynamically manage the intermediate voltage levels to ensure that at no point do transistor terminals experience voltage differences beyond their reduced tolerance, adapting to the constraints imposed by scaled transistor dimensions.
3Adaptability or versatility
If power source voltage is higher than nominal voltage to achieve higher output voltage, then voltage level shifting capability is improved, but transistor damage risk increases
Solution Approach 1:
The patent employs intermediary voltage generation circuits that create buffered intermediate voltage levels between the high power source voltage and the transistor operating voltages. These intermediaries allow the circuit to utilize higher power source voltages for extended voltage shifting range while preventing direct application of high voltage to transistor terminals, thus eliminating the damage risk.
Solution Approach 2:
The patent replaces direct electrical connection between high voltage source and transistor terminals with a controlled signal processing path. Instead of directly applying high voltage, the system uses controlled voltage generation and switching mechanisms that translate the high power source voltage into safe intermediate levels for transistor operation.
Data Source
AI summary
A voltage level shifter circuit, including: a first control circuit, arranged to receive an input voltage and generate a first control signal; a first pull-down circuit, arranged to determine whether to pull down a first output voltage to a first reference voltage according to the first control signal; a first pull-up circuit, arranged to determine whether to pull up the first output voltage to a second reference according to a first inverse output voltage; a second control circuit, arranged to generate a second control signal according to the first output voltage; a second pull-down circuit, arranged to determine whether to pull down a second output voltage to the second reference voltage according to the second control signal; and a second pull-up circuit, arranged to determine whether to pull up the second output voltage to a third reference voltage according to a second inverse output voltage.


