Voltage Mirror Circuit Reduces Static Offset in Current Sensing
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Solution Overview
Problem
Conventional current sensing methods in DC-DC converters incur significant power losses and introduce static offsets due to channel length modulation effects, which affect the accuracy and efficiency of current sensing.
Innovation Solution
A voltage mirror circuit is employed, comprising input and output current source transistors, gain transistors, and an output transistor, which reduces offset by mirroring bias currents and compensating for channel length modulation effects, allowing for lossless current sensing with high bandwidth and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional current sensing methods using resistors are employed, then current sensing is achieved, but significant power losses occur especially at high currents
Solution Approach 1:
The patent replaces the mechanical/resistive sensing method with a field-based sensing approach using MOSFET transistors. The channel length modulation effect in MOSFETs is exploited to sense current through voltage changes at the drain terminal, eliminating the need for power-dissipating resistors while maintaining sensing functionality.
Solution Approach 2:
The patent changes the sensing parameter from voltage drop across a resistor to voltage change at the drain terminal of a MOSFET due to channel length modulation. By utilizing the parameter relationship between drain voltage and channel length modulation, the system achieves lossless current sensing.
2Measurement precision
If conventional current sensing methods are used, then current sensing is achieved, but static offsets are introduced due to channel length modulation effects
Solution Approach 1:
The patent employs feedback mechanisms where the drain voltage of the sensing MOSFET is fed back to the gate through a feedback transistor. This feedback loop dynamically compensates for static offsets caused by channel length modulation, maintaining accurate current sensing despite the inherent physical effects.
Solution Approach 2:
The patent introduces intermediate transistors (feedback transistor and compensation transistor) that act as mediators between the sensing element and the output. These intermediary components transform and condition the signal to eliminate static offsets while preserving the current sensing information.
3Device complexity
If simple voltage mirror circuit is used, then circuit complexity is reduced, but offset compensation capability is limited
Solution Approach 1:
The patent merges multiple functions into a single integrated circuit block. The voltage mirror, feedback mechanism, and offset compensation are combined in one circuit configuration, reducing overall system complexity while maintaining precise offset compensation capabilities through the synergistic interaction of circuit elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces static offsets, maintains high gain bandwidth, and operates at low minimum supply voltages, improving the accuracy and efficiency of current sensing in DC-DC converters without additional amplifiers or complex architectures.
Implementation Method 1
The voltage mirror circuit may be configured to reduce an offset between the voltage level at the input node and the voltage level at the output node. In yet other words, the voltage mirror circuit may be configured to compensate possible channel length modulation effects incurred by the transistors comprised within the voltage mirror circuit.
Data Source
AI summary
A voltage mirror circuit, having an input node and an output node provides substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. The voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.