Voltage Mismatch Detection in Host Memory Controllers

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Solution Overview

Problem

Conventional information processing systems face failures due to mismatches in interface voltages between the information processing apparatus and nonvolatile storage devices, leading to unnecessary power consumption and battery duration loss, as they lack mechanisms to detect and address such voltage discrepancies.

Innovation Solution

An information processing apparatus equipped with a voltage switch, regulator, input/output driver, voltage detection circuit, and control unit that detects voltage mismatches between the apparatus and nonvolatile storage device, allowing for voltage adjustments to match the drive voltages and prevent system failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the interface voltage is lowered to 1.8 V for faster data transfer, then data transfer performance is improved, but system failures occur due to voltage mismatches with the 3.3 V NAND flash memory

Engineering Contradiction:
Improvedata transfer speedVSAvoidsystem reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the interface voltage level based on detection results. The host device switches between 1.8 V and 3.3 V interface voltages depending on whether a voltage mismatch is detected, allowing the system to optimize for speed when compatible and ensure reliability when incompatible devices are connected

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback through a voltage detection circuit that continuously monitors the interface voltage and provides information to the control unit. This feedback mechanism enables the system to detect voltage mismatches and automatically adjust the interface voltage to prevent system failures

Inventive Principle:
Principle #23Feedback

2Reliability

If voltage mismatch detection and adjustment mechanisms are added, then system reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a control unit that performs multiple functions: it manages voltage switching, coordinates with the voltage detection circuit, and handles the initialization and voltage change commands. This multi-functional approach consolidates complexity into a single component rather than adding separate dedicated circuits for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses an intermediary approach by introducing a control unit that mediates between the voltage detection circuit and the voltage switch. This intermediary component coordinates the detection and adjustment processes, simplifying the overall system architecture compared to direct coupling of detection and switching mechanisms

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9007864B2Information processing apparatus, nonvolatile storage device, information porcessing system and nonvolatile memory controller
Publication Date: 2015.04.14 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US9007864B2 patent drawing
  • US9007864B2 patent drawing
  • US9007864B2 patent drawing

AI summary

A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected to the voltage line and which outputs the first voltage or a second voltage that is lower than the first voltage, a host IO driver for driving a data line with the output of the host regulator as a power source, a host voltage detection circuit for detecting whether the voltage of the data line is the second voltage or a voltage that is higher than the second voltage, and a host control unit for detecting a mismatch of interface voltages between the host device and a memory card based on the output voltage of the host regulator and the detection result of the host voltage detection circuit.