Voltage-Mode Driver Preamplifier for Hard Disk Drive Write Operations
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Solution Overview
Problem
Conventional preamplifiers used in hard disk drives are costly, power-intensive, and require high supply voltages, making them inefficient for write operations in magnetic heads.
Innovation Solution
A voltage-mode driver preamplifier utilizing CMOS switches and a matching circuit with multiple voltage sources and resistors, operating at lower rail voltages (e.g., 4.5V and 0V), and employing cascode arrangements of MOS transistors to generate current waveforms for magnetic heads with reduced power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional preamplifier design is used, then write signal generation is achieved, but power consumption is high and supply voltage requirements are high
Solution Approach 1:
The patent changes the operating parameters by using lower supply voltages (4.5V and 0V rails) compared to conventional preamplifiers that require 8V or 10V. This parameter change directly reduces power consumption while maintaining the ability to generate the necessary current waveforms for magnetic head polarization and overshoot compensation
Solution Approach 2:
The patent replaces the conventional current-mode circuit implementation with a voltage-mode driver using CMOS switches. This substitution allows for more efficient voltage control and reduces the power requirements while achieving the same functional outcome of driving the magnetic head
2Ease of manufacture
If conventional preamplifier design is used, then write signal generation is achieved, but manufacturing cost is high
Solution Approach 1:
The patent employs standard CMOS technology and common electronic components (CMOS switches, resistors, capacitors, inductors) that are inexpensive and widely available, replacing the need for costly silicon-germanium processes. This approach maintains write signal performance while dramatically reducing manufacturing costs
3Use of energy by moving object
If lower supply voltages are used, then power consumption is reduced, but voltage headroom for signal generation is limited
Solution Approach 1:
The patent introduces an artificial magnetic field dimension by coupling the magnetic head to a transformer with a magnetically coupled secondary winding. This allows the generation of high-voltage signals (±10V to ±15V) across the transformer secondary even though the primary side operates at low voltages (4.5V and 0V), effectively solving the voltage headroom limitation while maintaining low power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient generation of write signals with reduced power consumption and cost, while maintaining effective polarization of magnetic elements, by using CMOS technology and lower supply voltages, thus improving upon the limitations of conventional preamplifiers.
Implementation Method 1
the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk
Data Source
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AI summary
A method for generating a current waveform reflecting write events fro a magnetic head preamplifier is provided. An input signal indicating a write event is received. A boost pulse and a write pulse corresponding with the write event are generated. A portion of a write signal with a half H-bridge (210-1) using the boost pulse and the write pulse is generated. This is generated by deactivating a first CMOS switch (SI) while activating a second CMOS switch (S2) to cause the portion of the write signal to transition from a first direct current (DC) voltage to a first peak voltage; after a first interval, deactivating the second CMOS switch (S2) while activating a third CMOS switch (S3) to cause the portion of the write signal to transition from the first peak voltage to a second DC voltage; after a second interval, deactivating the third CMOS switch (S3) while activating a fourth CMOS switch (S4) to cause the portion of the write signal to transition from the second DC voltage to a second peak voltage; and after a third interval, deactivating the fourth CMOS switch (S4) while activating the first CMOS switch (SI) to cause the portion of the write signal to transition from the second peak voltage to the first DC voltage.