Dynamic Power Supply Voltage Modulation for Hold Time Violations
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Solution Overview
Problem
Hold time violations in system on a chip (SOC) circuits occur due to differences in propagation delays between data paths, leading to premature switching and potential chip failures, which conventional solutions address by adding delay elements that increase die area and power consumption.
Innovation Solution
Modulating the power supply voltage to increase propagation delay in shorter data paths during the first half of a clock cycle and decrease it in longer data paths during the second half, using a multiplexer or oscillating circuit to control voltage levels, thereby preventing hold time violations without significantly affecting longer data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay elements are inserted in shorter data paths to increase propagation delay, then hold time violations are prevented, but die area and power consumption increase
Solution Approach 1:
The patent changes the power supply voltage parameter dynamically to control propagation delay. By lowering the voltage during the first half of the clock cycle, the propagation delay of shorter data paths is increased to prevent hold time violations, while avoiding the need for additional delay elements that would consume die area.
Solution Approach 2:
The patent applies periodic voltage modulation synchronized with the clock signal. The power supply voltage is lowered during the first half of the clock cycle and restored during the second half, creating a periodic action that prevents hold time violations only when needed, thereby avoiding continuous area and power penalties.
2Reliability
If delay elements are inserted in shorter data paths to increase propagation delay, then hold time violations are prevented, but power consumption increases
Solution Approach 1:
The patent changes the power supply voltage parameter dynamically to control propagation delay. By lowering the voltage during the first half of the clock cycle, the propagation delay of shorter data paths is increased to prevent hold time violations, while avoiding the need for additional delay elements that would consume die area.
Solution Approach 2:
The patent applies periodic voltage modulation synchronized with the clock signal. The power supply voltage is lowered during the first half of the clock cycle and restored during the second half, creating a periodic action that prevents hold time violations only when needed, thereby avoiding continuous area and power penalties.
3Reliability
If power supply voltage is decreased to increase propagation delay of shorter data paths, then hold time violations are reduced, but propagation delay of longer data paths is also affected
Solution Approach 1:
The patent applies periodic voltage modulation synchronized with the clock signal. The power supply voltage is lowered during the first half of the clock cycle and restored during the second half, creating a periodic action that prevents hold time violations only when needed, thereby avoiding continuous area and power penalties.
Solution Approach 2:
The patent makes the power supply voltage dynamic rather than static. By modulating the voltage in sync with the clock signal, the system adapts the propagation delay characteristics dynamically - increasing delay for shorter paths when needed while restoring normal operation for longer paths during the second half of the clock cycle.
Data Source
AI summary
Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.