Voltage Multiplier Capacitance Boost for Low-Ripple High Output
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Solution Overview
Problem
Existing voltage multipliers struggle to efficiently generate a voltage higher than twice the supply voltage while maintaining a stable and efficient output.
Innovation Solution
A device with a voltage multiplier that includes capacitive elements and switch units controlled by clock signals, enhancing capacitance through specific well region constructions and diode connections, allowing for the generation of a load voltage twice the supply voltage with minimal ripple and high efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional voltage multipliers are used to generate voltage higher than twice the supply voltage, then the output voltage can be increased, but the efficiency deteriorates and ripple voltage increases
Solution Approach 1:
The voltage multiplier is divided into multiple stages (first voltage multiplier stage, second voltage multiplier stage) with separate capacitive elements and switch units. Each stage operates independently with its own clock signal, allowing efficient voltage multiplication while maintaining low ripple voltage. The segmentation enables the system to achieve twice the supply voltage with high efficiency (91%-99%) and small ripple voltage (20-30 mV).
Solution Approach 2:
The patent employs periodic clock signals (first clock signal, second clock signal) to control the switch units in each voltage multiplier stage. The periodic switching action enables efficient charge transfer and voltage multiplication. The clock signals are synchronized to ensure proper timing, achieving high efficiency operation with minimal energy loss and reduced ripple voltage through controlled periodic charging and discharging cycles.
2Power
If conventional voltage multipliers are used to generate voltage higher than twice the supply voltage, then the output voltage can be increased, but the ripple voltage increases
Solution Approach 1:
The voltage multiplier is divided into multiple stages (first voltage multiplier stage, second voltage multiplier stage) with separate capacitive elements and switch units. Each stage operates independently with its own clock signal, allowing efficient voltage multiplication while maintaining low ripple voltage. The segmentation enables the system to achieve twice the supply voltage with high efficiency (91%-99%) and small ripple voltage (20-30 mV).
Solution Approach 2:
The patent implements a feedback mechanism where the output of each voltage multiplier stage feeds into the next stage. The capacitive elements store charge and provide feedback to maintain stable output voltage. This feedback approach ensures that the ripple voltage remains minimal (20-30 mV) while achieving the desired high output voltage (twice the supply voltage) with high stability.
3Loss of energy
If capacitance is increased to improve voltage multiplier efficiency, then the efficiency improves, but the physical size increases
Solution Approach 1:
The patent optimizes the capacitance values of the capacitive elements in each voltage multiplier stage to achieve high efficiency without excessive physical size. By carefully selecting capacitance parameters and configuring the multi-stage architecture, the system achieves 91%-99% efficiency while maintaining a compact form factor. The parameter optimization allows efficient operation with minimal ripple voltage (20-30 mV) without requiring large physical capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a load voltage approximately 91% to 99% of twice the supply voltage with a small ripple voltage of 20-30 mV within 8 μs, improving efficiency by up to 12% without increasing physical size.
Implementation Method 1
A device with a high efficiency voltage multiplier includes a capacitive element coupled between first and second nodes
Implementation Method 2
enhancing capacitance through specific well region constructions and diode connections
Data Source
AI summary
A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.