Voltage Multiplier-Assisted PFC Circuit for Low-Voltage Loss Reduction
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Solution Overview
Problem
Wide input power factor correction (PFC) circuits exhibit lower efficiency at the low end of the input voltage range, leading to increased copper losses due to significant root mean square (RMS) currents, which can cause current spikes and reduce overall power supply efficiency.
Innovation Solution
Incorporating a voltage multiplier circuit, such as a bridgeless PFC circuit with a bidirectional switch and capacitors, to reduce the duty cycle and operating frequency of the PFC circuit, thereby reducing losses and increasing efficiency by enabling voltage doubling or tripling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a power factor correction circuit is used to improve the power factor of a power system, then the power factor is improved, but power losses increase and overall efficiency is reduced
Solution Approach 1:
The PFC circuit is divided into two independent full-bridge circuits operating at different frequencies. The first full-bridge circuit operates at a lower frequency to reduce switching losses, while the second full-bridge circuit operates at a higher frequency to maintain compact size. This segmentation allows each circuit to be optimized for its specific function, reducing overall power losses while maintaining power factor correction capability.
Solution Approach 2:
The patent employs periodic switching actions at different frequencies in the two full-bridge circuits. The first circuit switches at a lower frequency during certain periods to minimize switching losses, while the second circuit switches at a higher frequency during other periods to maintain compact transformer and inductor sizes. This periodic action at different frequencies reduces cumulative power losses while achieving effective PFC.
2Adaptability or versatility
If the input voltage is at the low end of the input voltage range, then the PFC circuit operates, but efficiency decreases due to increased copper losses from significant RMS currents
Solution Approach 1:
The control circuit dynamically adjusts the operating parameters of the PFC circuit based on the input voltage level. When operating at the low end of the input voltage range, the control circuit modifies the duty cycles and switching frequencies of the two full-bridge circuits to optimize performance. This dynamic adjustment reduces RMS currents and associated copper losses while maintaining adaptability across the full input voltage range.
3Volume of moving object
If the switching frequency is increased to reduce component size, then the power supply size is reduced, but power losses increase
Solution Approach 1:
The power supply is segmented into two full-bridge circuits with different switching frequencies. The first circuit uses a lower frequency to minimize switching and conduction losses, while the second circuit uses a higher frequency to reduce the size of magnetic components. This segmentation allows the system to achieve a compact overall size without incurring excessive power losses from high-frequency switching.
Solution Approach 2:
The patent changes the switching frequency parameter between the two full-bridge circuits. The first circuit operates at a lower frequency to reduce losses, while the second circuit operates at a higher frequency to reduce component size. By implementing different frequency parameters in parallel circuits, the system achieves both compact size and acceptable efficiency.
Data Source
AI summary
An example controller includes: an absolute value circuit having a voltage output and first and second power inputs, the first and second power inputs adapted to be coupled to an alternating current (AC) power source, and a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the voltage output, the second comparator input adapted to be coupled to an output terminal of a power factor correction (PFC) circuit, and the comparator output adapted to be coupled to a control input of the PFC circuit.