Voltage Reconciliation in Multi-Level Power Managed IC Systems
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Solution Overview
Problem
In multi-level power managed IC systems, conflicts arise when power-state combinations in new designs clash with those of reused blocks, leading to undesirable elimination of critical power-state information, which can result in improper IC device operation, and current solutions require manual modifications that are risky and time-consuming.
Innovation Solution
An automated method within EDA tools to identify and reconcile voltage level and power-state combination conflicts by analyzing Power-State Tables, ensuring compatible corrections and flagging incompatible conflicts for coordinated solutions, thereby avoiding manual corrections and ensuring reliable IC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If EDA tools automatically remove conflicting power-state combinations to resolve voltage level conflicts, then device complexity is reduced, but reliability deteriorates due to elimination of required power-state combinations
Solution Approach 1:
The patent introduces an intermediary voltage reconciliation process that acts as a mediator between block-level and top-level UPF design files. This intermediary mechanism identifies and resolves voltage level conflicts through automated reconciliation algorithms, adjusting voltage values to be consistent across hierarchy levels while preserving all required power-state combinations, thus avoiding the need to remove critical power states.
Solution Approach 2:
The patent applies preliminary action by performing voltage reconciliation before the final power-state combination validation. The system proactively identifies and resolves voltage conflicts in advance through automated algorithms that analyze voltage relationships across hierarchical levels, ensuring that no required power-state combinations are eliminated during subsequent processing.
2Adaptability or versatility
If IC designers manually modify reused block design files to resolve power-state conflicts, then adaptability is improved, but productivity deteriorates due to time-consuming manual changes
Solution Approach 1:
The patent implements self-service by enabling the EDA tool to automatically resolve voltage level conflicts without requiring manual designer intervention. The automated reconciliation process analyzes voltage relationships, identifies conflicts, and applies corrections autonomously, allowing the system to adapt power-state combinations while maintaining productivity. This eliminates the need for designers to manually modify block design files.
Solution Approach 2:
The patent applies parameter changes by automatically adjusting voltage level parameters in the UPF design files through reconciliation algorithms. The system modifies voltage values to resolve conflicts between block-level and top-level specifications, maintaining adaptability while avoiding manual intervention and preserving development productivity.
3Ease of operation
If manual modification of blocks is performed to resolve power-state conflicts, then ease of operation is improved, but reliability deteriorates due to risky changes that may not satisfy IC design
Solution Approach 1:
The patent implements feedback by creating a closed-loop verification system that continuously checks whether resolved power-state combinations satisfy the original IC design requirements. The automated reconciliation process provides feedback mechanisms that validate each voltage adjustment against design specifications, ensuring that ease of operation does not compromise the reliability and validity of power-state combinations.
Solution Approach 2:
The patent introduces an intermediary automated reconciliation process that acts as a reliable mediator between conflicting specifications. This intermediary system ensures that all modifications to power-state combinations are performed according to strict rules and validations, maintaining reliability while providing ease of operation through automation. The intermediary verifies that changes satisfy IC design requirements before accepting them.
Data Source
AI summary
A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both initial power supply voltage values and reconciled/revised voltage values, which are determined by the main driver voltage levels of each power supply. Initial supply relationships generated using the initial PSTs are then compared with final supply relationships generated using the reconciled PSTs, whereby conflicts are identified when one or more initial supply relationship fails to match a final supply relationship, or when one or more final supply relationship fails to match an initial supply relationship.