Voltage Reference Buffer Circuit with Complementary Transistors
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Solution Overview
Problem
Existing voltage reference buffer circuits have limited driving capability due to the use of a single driving component, which affects the precision, settling speed, and power consumption, and often require overvoltage protection mechanisms that do not enhance driving capacity during normal operation.
Innovation Solution
A voltage reference buffer circuit utilizing multiple driving components of different types, such as NMOS and PMOS transistors, to concurrently provide driving assistance and control current between the reference voltage output terminal and load, enhancing current sourcing and sinking capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single driving component is used at the reference voltage output terminal, then the circuit complexity is reduced, but the driving capability especially current sink capability becomes weak
Solution Approach 1:
The patent combines multiple driving components (first and second driving components of different transistor types) at the reference voltage output terminal to work simultaneously. This merging approach enhances the driving capability and current sink capability while maintaining reasonable circuit complexity through systematic design
2Ease of manufacture
If a single type of transistor is used at the output terminal, then the manufacturing process is simplified, but the settling speed of reference voltage becomes slow
Solution Approach 1:
The patent employs asymmetric design by using different types of transistors (NMOS and PMOS) with complementary characteristics at the output terminal. This asymmetry allows each transistor type to excel in different operating conditions, thereby improving settling speed while maintaining manufacturing feasibility through standard CMOS processes
3Stability of the object's composition
If limited loop bandwidth is used in LDO, then the stability is improved, but the response to rapid voltage or load changes becomes delayed causing transient response issues
Solution Approach 1:
The patent implements preliminary action by proactively managing voltage transitions through complementary transistor pairs that can quickly respond to load changes before transient issues occur. The circuit is designed to anticipate and counteract potential voltage surges or drops, maintaining stability while improving response speed
4Speed
If output voltage is allowed to change rapidly, then the response speed is improved, but transient voltage changes may damage system components
Solution Approach 1:
The patent applies preliminary anti-action by designing the complementary transistor configuration to preemptively counteract harmful transient voltage changes. The circuit structure inherently prevents voltage surges that could damage components while maintaining fast response capability, eliminating the need for separate protection circuits
Data Source
AI summary
Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.