Voltage Reference Circuit Using NMOS Threshold Difference

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Solution Overview

Problem

Existing voltage reference circuits require a large number of transistors, significant chip area, and are costly, with precision being challenging due to transistor matching issues and variations in threshold voltages, making them inefficient for high precision applications.

Innovation Solution

A voltage reference circuit design utilizing a first and second current mirror with NMOS and PMOS transistors, an amplifier, and a feedback loop, where the threshold voltage difference between NMOS transistors and the ratio of currents through PMOS transistors are maintained to reduce the number of transistors required and improve accuracy, while the amplifier's large input offset allows for smaller size and reduced sensitivity to power supply voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple MOSFET transistors are used to achieve high precision voltage reference, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage reference precisionVSAvoidnumber of transistors
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates unnecessary transistors from the voltage reference circuit. By removing redundant current mirror transistors and simplifying the circuit topology, the design achieves high precision voltage reference using fewer transistors, directly resolving the contradiction between measurement precision and device complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes transistors perform multiple functions simultaneously. For example, certain transistors serve both as part of the voltage reference generation and as compensation elements, reducing the total transistor count while maintaining precision requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If transistor size is increased to minimize manufacturing variation, then manufacturing precision is improved, but area occupied increases

Engineering Contradiction:
Improvetransistor matching accuracyVSAvoidchip area
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent segments the voltage reference function across fewer transistors, allowing each transistor to be smaller while maintaining overall precision. The circuit architecture divides the reference voltage generation into functional segments that require smaller individual transistor sizes compared to traditional designs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes critical circuit parameters such as bias currents, voltage levels, and transistor aspect ratios to achieve precise matching with smaller transistor sizes. By optimizing these parameters, the design reduces the required transistor area while maintaining manufacturing precision

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If more transistors are used to achieve accurate matching, then measurement precision is improved, but cost increases

Engineering Contradiction:
Improvevoltage reference accuracyVSAvoidmanufacturing cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent removes unnecessary transistors from the circuit, directly reducing manufacturing cost while maintaining voltage reference accuracy through optimized circuit topology that achieves precision with fewer components

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses standard, readily available transistor designs and processes rather than specialized expensive components, achieving high precision through clever circuit architecture rather than expensive hardware

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

4Measurement precision

If transistor matching is improved to reduce threshold voltage variation, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage matchingVSAvoidcircuit structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs asymmetric transistor sizing and biasing strategies to compensate for threshold voltage variations without requiring symmetric matching. By using different transistor dimensions and bias conditions, the circuit achieves accurate voltage reference while simplifying the overall structure

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent incorporates feedback mechanisms that automatically compensate for transistor threshold voltage variations. The feedback loop adjusts operating points to maintain precise voltage reference, reducing the need for tight transistor matching and simplifying circuit structure

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9383764B1Apparatus and method for a high precision voltage reference
Publication Date: 2016.07.05 DIALOG SEMICONDUCTOR (UK) LTD
  • US9383764B1 patent drawing
  • US9383764B1 patent drawing
  • US9383764B1 patent drawing

AI summary

An apparatus and method for a voltage reference circuit with improved precision. The voltage reference circuit utilizes threshold voltage difference between a pair of MOSFETs. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, includes a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold voltage is not equal to said second NMOS transistor threshold voltage, a second current mirror with a first PMOS transistor, a second and third PMOS transistor configured to be coupled to said power supply node, a current source configured to be provide current to said second current mirror, an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor and said second NMOS transistor and, a feedback loop configured to be the output of said amplifier.