Voltage Regulator Bypass Transistor Low Dropout
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Solution Overview
Problem
Voltage regulator circuits face challenges in achieving low dropout voltage due to high input-to-output voltage drop in N-type followers and limited voltage swing capability in P-type followers, leading to stability and bandwidth issues, especially in low voltage applications.
Innovation Solution
Incorporating a bypass transistor in the output voltage error control loop to extend the operating range of the output transistor by bypassing the gate-source junction of the driver FET when the gate-to-source voltage becomes limiting, allowing the error amplifier to drive the output FET closer to ground or supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an N-type source-follower is used as driver for the output FET, then the circuit can provide efficient regulation, but the input-to-output voltage drop Vgs becomes high
Solution Approach 1:
A bypass transistor is introduced as an intermediary component in parallel with the driver FET. This bypass transistor acts as a mediator that provides an alternative current path when the driver FET's gate-source voltage becomes limiting, thereby extending the output voltage swing capability without compromising regulation efficiency
Solution Approach 2:
The circuit dynamically switches between the driver FET and the bypass transistor based on operating conditions. The bypass transistor is activated when the driver FET approaches its voltage limitation, allowing the circuit to adapt its driving mechanism to maintain optimal performance across the extended voltage range
2Ease of operation
If a P-type follower is used as driver for the output FET, then the voltage swing range is extended, but the circuit cannot drive the output FET down close to ground
Solution Approach 1:
The invention merges the advantages of both N-type and P-type followers by combining them in a complementary configuration. The driver FET (N-type) handles low voltage operation close to ground, while the bypass transistor (P-type) extends the upper voltage swing capability, creating a hybrid solution that achieves both goals
3Ease of operation
If a differential amplifier in unity gain configuration is used, then a wider voltage range can be driven, but an extra OP-amp increases complexity, footprint area and cost
Solution Approach 1:
Instead of using a complete differential amplifier with OP-amp, the invention uses a simplified bypass transistor configuration that copies the essential functionality of extending voltage range. This simplified approach achieves the voltage extension goal without the complexity, footprint, and cost of a full OP-amp implementation
4Ease of operation
If an OP-amp is added to drive wider voltage range, then voltage swing capability is improved, but an additional pole is introduced leading to stability problems and deteriorated speed and bandwidth performance
Solution Approach 1:
The invention extracts only the necessary voltage extension functionality from the OP-amp/differential amplifier and implements it through a simple bypass transistor. By removing the unnecessary OP-amp components, the additional pole that causes stability problems is eliminated, while the essential voltage swing extension capability is preserved
Data Source
AI summary
A low dropout voltage regulator (100; 300) comprises a supply input terminal (102; 302) for connecting a supply voltage (VDD) and an output terminal (104; 304) for providing a regulated output voltage (V0), a reference voltage source (130; 330); and an output voltage monitor (120; 320). An error amplifier (132; 332) has an output (138; 338) supplying an error signal (Verr) in response to deviations of the regulated output voltage (Vout) from a desired target output voltage value (V0) at the output terminal (104; 304). A power output FET (110; 310), has a drain-source channel connected between the supply input terminal (102; 302) and the output terminal (104; 304) of the voltage regulator, and a gate terminal (116; 316). The gate terminal of the power output FET (110; 310) is controlled by the error amplifier (132; 332) via a driver FET (140; 340) in such a way that any deviations of the regulated output voltage (Vout) from a desired target output voltage value (V0) are minimized. The regulator further comprises a bypass FET (150; 350) of an n-conductivity type, which has a source terminal (154; 354) connected to the gate terminal (142; 342) of the driver FET (140; 340), a drain terminal (156; 356) connected to the source terminal (112; 312) of the driver FET (140; 340), and a gate (152; 352) connected to a bias voltage source (158; 358). The bias voltage is determined such that the bypass FET (150; 350) begins conducting when the source voltage of the driver FET (140; 340) cannot be further reduced by application of the error signal (Verr) to its gate towards the drain potential, due to the inherent gate-source voltage drop (Vgs) of the driver FET (140; 340).