Voltage Regulator Clock Override for Load Transients

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Solution Overview

Problem

Voltage regulators face challenges in providing adequate power supply to microprocessors with varying load demands, leading to potential voltage droops due to rapid changes in power requirements.

Innovation Solution

Implementing a multi-phase switching voltage regulator system with clock override capability, where the core clock signal drives the voltage regulator switches at a higher frequency ahead of anticipated load changes to minimize droop, and using a distributed architecture with domain VRs to manage power delivery efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the voltage regulator operates at normal drive frequency, then power efficiency is maintained, but voltage droop occurs during rapid load changes

Engineering Contradiction:
Improvevoltage stabilityVSAvoidresponse speed to load changes
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary action by detecting impending load changes through clock signal monitoring and proactively increasing the switch drive frequency before the actual load change occurs. This anticipatory mechanism allows the voltage regulator to prepare the power delivery system in advance, preventing voltage droop before it happens rather than reacting after the droop occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The voltage regulator employs dynamic operation by continuously adjusting the switch drive frequency based on real-time load conditions. The system transitions from a static fixed-frequency operation to a dynamic variable-frequency operation, where the frequency is modulated according to the detected load demands, enabling optimal performance across varying operating conditions.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the switch drive frequency is increased to respond to load changes, then voltage droop is reduced, but power consumption increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system applies partial action by increasing the switch drive frequency only to the extent necessary to prevent voltage droop during detected load changes, rather than maintaining a constantly high frequency. The frequency modulation is proportional to the detected load demand, applying just enough additional switching activity to maintain stability without excessive energy consumption during steady-state operation.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If a single voltage regulator is used, then device complexity is low, but adequate power supply during rapid load changes cannot be guaranteed

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidregulator architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The voltage regulator system is segmented into multiple parallel switching regulators, each capable of independent operation. This segmentation allows the total power delivery capability to be distributed across multiple units, with each regulator handling a portion of the load. The modular segmented architecture provides the necessary power delivery headroom for rapid load changes while keeping individual regulator complexity manageable.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8099619B2Voltage regulator with drive override
Publication Date: 2012.01.17 INTEL CORP
  • US8099619B2 patent drawing
  • US8099619B2 patent drawing
  • US8099619B2 patent drawing

AI summary

Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When the functional block is about to require an increased level of power, the associated clock is provided to drive the at least one regulator switches overriding their normal drive signal, which has a lower frequency. Thus, the switches are driven at a higher frequency sufficiently prior to (e.g., just ahead of) the load change to reduce the amount of droop that would otherwise occur.