Voltage Regulator Control Circuit Slew Rate Reference Signal

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Solution Overview

Problem

Traditional methods for obtaining a reference signal from a pulse width modulation signal in voltage regulators for processors result in significant ripple and jitter, leading to increased power loss.

Innovation Solution

A method and control circuit that measure the duty cycle of a pulse width modulation signal to calculate a target voltage and provide a reference signal, restricting its monotone change to maintain the reference signal within a predetermined range, thereby reducing ripple and jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If traditional method is used to obtain reference signal from PWM signal, then the voltage regulator can provide output voltage, but the reference signal has large ripple and jitter which increases power loss

Engineering Contradiction:
Improvepower lossVSAvoidreference signal stability
Core Design Contradiction:
Loss of energyVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by measuring the duty cycle of the PWM signal in advance and using it to generate a stable reference signal before voltage regulation. The duty cycle measurement and reference signal generation occur beforehand, allowing the system to establish a stable reference that minimizes ripple and jitter before the voltage regulation process begins, thereby reducing power loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary element - the duty cycle measurement - that mediates between the PWM signal and the reference signal generation. By measuring the duty cycle as an intermediate parameter and using it to control the reference signal, the system achieves better stability and reduces ripple and jitter, thereby reducing power loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the reference signal is allowed to change freely with duty cycle variations, then the voltage regulator responds quickly to load changes, but the reference signal exhibits large ripple and jitter

Engineering Contradiction:
Improveresponse speedVSAvoidreference signal stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The patent applies partial action by selectively controlling when the reference signal changes. Instead of allowing the reference signal to change freely with every PWM duty cycle variation, the system uses the duty cycle measurement to partially control the reference signal updates. This selective approach maintains necessary responsiveness while filtering out excessive changes that cause ripple and jitter.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter used to control the reference signal from direct PWM duty cycle following to duty cycle measurement-based control. By measuring the duty cycle and using this measured parameter to control the reference signal, the system achieves a balance between response speed and stability, reducing ripple and jitter while maintaining adequate response to load changes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10523107B2Control circuit for voltage regulator with slew rate controlled reference signal generating and associated method
Publication Date: 2019.12.31 CHENGDU MONOLITHIC POWER SYST
  • US10523107B2 patent drawing
  • US10523107B2 patent drawing
  • US10523107B2 patent drawing

AI summary

A method for controlling a voltage regulator is receiving a voltage identification code which has a pulse width modulation signal, providing a duty signal via measuring a duty cycle of the pulse width modulation signal, calculating a target voltage based on the duty signal, providing a reference signal based on the duty signal and the target voltage. If it is judged that the duty cycle of the pulse width modulation signal increases, the reference signal is restricted increasing or keeping its value without decreasing, and if it is judged that the duty cycle of the pulse width modulation signal decreases, the reference signal is restricted decreasing or keeping its value without increasing.