Voltage Regulator Gate Resistor Dead Time Reduction
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Solution Overview
Problem
Conventional switching-mode voltage regulators experience inefficiencies due to voltage spikes and excessive dead time, which are costly to address with existing solutions like Schottky diodes and R-C snubbers.
Innovation Solution
Incorporating a tuned gate resistance in the control path of the sync switch to reduce dead time and voltage spikes, allowing the sync MOSFET to conduct during spikes and absorb excess energy, thereby reducing power losses and enabling the use of lower voltage rated devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional approaches (Schottky diode, R-C snubber, soft recovery) are used to reduce reverse recovery current and voltage spikes, then voltage spike suppression is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the electrical parameters of the sync MOSFET by introducing a gate resistor (Rg) and gate capacitor (Cg) network that modifies the gate voltage waveform. This transforms the sharp, abrupt gate voltage transition into a controlled, rounded transition, thereby changing the switching characteristics and reducing voltage spikes without requiring expensive external suppression components.
Solution Approach 2:
The patent makes the sync MOSFET self-regulating by incorporating the gate resistor and capacitor directly into the MOSFET's gate structure. The device automatically controls its own switching behavior through the RC time constant formed by these components, eliminating the need for external Schottky diodes, R-C snubbers, or soft recovery circuits to suppress voltage spikes.
2Object-affected harmful factors
If dead time between sync switch turn-off and control switch turn-on is increased, then voltage spikes are reduced, but efficiency deteriorates due to excessive dead time
Solution Approach 1:
The patent introduces dynamic control of the gate voltage waveform through the RC network, which creates a time-dependent voltage transition. The gate voltage rises and falls exponentially rather than instantaneously, allowing the switching transition to be dynamically optimized to reduce both voltage spikes and dead time simultaneously.
Solution Approach 2:
The gate capacitor begins charging through the gate resistor before the gate voltage reaches the threshold for MOSFET turn-on. This preliminary charging action prepares the gate for a controlled transition, reducing the abruptness of switching and thereby reducing voltage spikes without requiring excessive dead time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances efficiency by minimizing dead time and voltage spikes, reducing manufacturing costs and power consumption while maintaining system reliability.
Implementation Method 1
the reverse recovery current of the body diode of the sync MOSFET allows excess current to flow when the sync MOSFET is turned off
Implementation Method 2
the tuned gate resistance may reduce anticipated voltage spikes during a turn-on time of the control switch
Data Source
AI summary
A voltage regulator includes an active control switch, an active sync switch, a driver circuit, and a gate resistor. The active control switch is coupled between an input voltage line and an input of an energy storage device. The active sync switch is coupled to the input of the energy storage device. The driver circuit is coupled to the control and sync switches to alternately drive each of the control and sync switches into a conducting state to produce a regulated voltage at an output of the energy storage device. The gate resistor is coupled in series within a control path of the sync switch. The gate resistor has a resistance value that is tuned to reduce an anticipated dead time between a turn-off time of the sync switch and a turn-on time of the control switch.