Supply Voltage Regulator With Node Initialization and HV Protection
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Solution Overview
Problem
Supply voltage regulator (SVR) circuits face a trade-off between achieving low quiescent current (Iq) and fast response time, with additional challenges such as high-voltage protection and robust startup, which are often contradictory and difficult to achieve simultaneously.
Innovation Solution
The SVR circuit architecture incorporates multiple sub-circuits, including a node initialization sub-circuit for startup, high-voltage protection sub-circuit, fast turn-off sub-circuit, and fast start-up sub-circuit, utilizing a combination of NMOS and PMOS transistors, diodes, and current sources to manage node initialization, protect against high voltages, and rapidly respond to voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SVR circuit design is used, then the circuit can provide voltage regulation, but the quiescent current is high and response time is slow
Solution Approach 1:
The SVR circuit is divided into multiple functional sub-circuits: a control sub-circuit for voltage regulation, a fast turn-on sub-circuit for rapid startup, a fast turn-off sub-circuit for quick response to voltage changes, and a node initialization sub-circuit for proper initialization. Each sub-circuit uses tailored transistor configurations (NMOS and PMOS) optimized for its specific function, allowing low quiescent current in normal operation while enabling fast response when needed.
2Reliability
If high-voltage protection is added to the SVR circuit, then the circuit gains protection capability, but the device complexity increases
Solution Approach 1:
The high-voltage protection function is merged into the existing control sub-circuit by adding a voltage protection sub-circuit that shares nodes and transistors with the control function. The diode stack connected to node 282 and the protection transistors (NMOS 240-244, PMOS 215) are integrated with the control logic, allowing voltage protection without requiring entirely separate protection circuits, thus limiting the increase in complexity.
3Speed
If fast turn-on and fast turn-off sub-circuits are added, then the response time is reduced, but the device complexity increases
Solution Approach 1:
The fast turn-on sub-circuit pre-charges nodes (particularly node 277 via current source 255 and capacitor 256) before full operation is needed. The fast turn-off sub-circuit pre-positiones transistors (NMOS 248-249, PMOS 247) in states that enable rapid response. This preliminary action allows the circuit to transition quickly between states without requiring complex real-time control mechanisms during the actual switching event.
4Reliability
If node initialization sub-circuit is implemented, then false power-on reset activations are minimized, but the device complexity increases
Solution Approach 1:
The node initialization sub-circuit proactively sets nodes (278, 279, 275, 277) to their correct initial states before the regulator begins normal operation. By pre-establishing proper voltage levels on these nodes through dedicated initialization transistors (NMOS 232-235, PMOS 236-237) and capacitors (228, 256), the circuit prevents false power-on reset conditions from occurring, eliminating the need for complex detection and correction logic that would otherwise be required.
Data Source
AI summary
A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.