Digital Voltage Regulator PID Optimization for Output Impedance
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Solution Overview
Problem
Conventional switching voltage regulators face challenges in achieving a phase margin of at least 60 degrees, leading to peaks or bumps in the output impedance response, especially when operating at low switching frequencies, which affects the transient response and efficiency.
Innovation Solution
The method involves determining and re-determining PID coefficients for a digital voltage regulator controller to satisfy gain and phase margin targets, and optimizing control loop coefficients to flatten the output impedance response across the bandwidth, using a system model and iterative optimization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control bandwidth is set to match ESR zero in conventional AVP design, then bandwidth utilization is maximized, but peaks or bumps occur in the output impedance curve
Solution Approach 1:
The patent modifies the control bandwidth parameter to be lower than the ESR zero frequency, which prevents the formation of peaks or bumps in the output impedance curve. This parameter change trades some bandwidth utilization for a flatter, more reliable output impedance response across the operating range.
2Loss of energy
If very low switching frequency is used to achieve greater efficiency, then energy loss is reduced, but phase margin of at least 60 degrees cannot be obtained
Solution Approach 1:
The patent changes the control bandwidth parameter to be lower than the ESR zero frequency, which enables achieving adequate phase margin (at least 60 degrees) even when operating at very low switching frequencies. This allows the system to maintain low switching losses while ensuring stable operation with sufficient phase margin.
Data Source
AI summary
Control loop coefficients for a digital voltage regulator controller are determined by determining PID (proportional-integral-derivative) coefficients that satisfy gain and phase margin targets for a digital voltage regulator controller, as a function of a plurality of system parameters for the digital voltage regulator controller, and re-determining one or more of the PID coefficients to flatten an output impedance response of the digital voltage regulator controller for frequencies below a bandwidth of the digital voltage regulator controller.