Voltage Regulator Transient Response Control
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Solution Overview
Problem
Existing voltage regulators with transient response improvement circuits tend to oscillate when returning to normal current levels or switching PMOS transistors from on to off, which affects the stability of output voltage.
Innovation Solution
A voltage regulator design incorporating a first amplifier for detecting undershoot, a second amplifier for detecting overshoot, a first constant current circuit to increase bias current for a specific time, a second constant current circuit to increase bias current further but for a shorter duration, and a switch circuit to manage the output transistor gate, ensuring improved transient response without oscillation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bias current is increased to improve transient response, then the slew rate and response speed are improved, but oscillation occurs when returning to normal current levels
Solution Approach 1:
The patent applies periodic action by using two distinct time periods for bias current increase: a first time period where bias current is increased by a first amount, and a second time period (shorter than the first) where bias current is increased by a second amount. This staged periodic approach allows the system to respond dynamically to transient conditions while automatically returning to normal operation, preventing oscillation that would occur with continuous high current.
Solution Approach 2:
The patent implements dynamics by making the bias current adjustable and time-dependent rather than fixed. The bias current circuit responds dynamically to transient conditions (overshoot/undershoot detection) and automatically adjusts the current level based on the specific time period, enabling the system to adapt its characteristics to match operational requirements while maintaining stability.
2Reliability
If PMOS transistor is switched on quickly to suppress overshoot, then the transient response is improved, but oscillation occurs when switching from on to off
Solution Approach 1:
The patent uses periodic action by defining specific time periods for PMOS transistor operation. The transistor is activated during transient conditions (overshoot or undershoot) and automatically deactivated after the predetermined first time period expires, ensuring controlled switching that prevents oscillation while maintaining effective transient suppression.
Solution Approach 2:
The patent implements feedback through detection circuits that monitor output voltage conditions (overshoot/undershoot) and control the PMOS transistor and bias current circuits accordingly. When transient conditions are detected, the system activates the appropriate circuits; when conditions normalize, the system deactivates them, creating a closed-loop feedback mechanism that maintains stability.
3Reliability
If the bias current is increased for a longer duration, then transient response improvement is maintained, but the recovery time to normal operation is extended
Solution Approach 1:
The patent applies periodic action by implementing two distinct time periods with different current levels. The first time period provides extended bias current for sustained transient improvement, while the second (shorter) time period enables faster recovery to normal operation. This staged temporal approach optimizes both transient response maintenance and recovery speed.
Solution Approach 2:
The patent uses dynamics by making the bias current level time-dependent, transitioning from a first current level during the first time period to a second current level during the second time period. This dynamic adjustment allows the system to maintain improved transient response when needed while automatically recovering to normal operation efficiently.
Data Source
AI summary
Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.