Memory Voltage Selector Timing to Prevent MOSFET Overvoltage
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Solution Overview
Problem
Integrated circuit memory systems face challenges in controlling voltage supply during polarity transitions, leading to excessive voltages across MOSFET devices, which can cause damage and affect the reliability of memory operations.
Innovation Solution
A timing control circuit is implemented using AND and OR gates with feedback loops, along with voltage selectors and level shifters, to manage the transition between positive and negative high voltages, ensuring that no MOSFET device is subjected to more than 5.5V during polarity transitions, by delaying the transitions of voltage selectors to prevent simultaneous application of high voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage selectors transition simultaneously between positive and negative high voltages, then polarity switching speed is improved, but excessive voltage exceeds MOSFET breakdown voltage causing device damage
Solution Approach 1:
The patent applies preliminary action by delaying the transition of one voltage selector until after the other voltage selector has already transitioned. Specifically, the first voltage selector transitions before the second voltage selector, ensuring that at any moment during the transition period, only one voltage selector is switching. This prevents the simultaneous application of positive and negative high voltages that would otherwise cause excessive voltage across the MOSFET device.
2Reliability
If voltage transition timing is controlled to prevent excessive voltage, then MOSFET reliability is improved, but transition timing complexity increases
Solution Approach 1:
The patent employs feedback mechanisms through delay circuits that monitor the transition state of voltage selectors and adjust the timing of subsequent transitions. The delay circuit receives signals from the voltage selectors and generates delayed feedback signals that control when the next voltage selector should transition, ensuring proper sequencing while automatically adapting to the actual transition timing of the circuit components.
Data Source
AI summary
A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and −4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and −4.5V.