Voltage Level Shifter With Voltage-Drop Path for Faster Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage level shifters experience noise and 'jiggle' in output voltage due to competition between PMOS and NMOS transistors, leading to delayed transition times and distortion, especially when input voltage is noisy and transistors operate near threshold voltages, requiring faster switching speeds and reduced gate thickness for NMOS transistors.
Innovation Solution
The proposed voltage level shifter incorporates a voltage drop circuit with thinner gate NMOS transistors and a path division circuit to isolate current paths between pull-up and pull-down circuits, reducing noise and 'jiggle' by minimizing competition between transistors, and includes a pull-up circuit with PMOS transistors and a pull-down circuit with NMOS transistors to efficiently shift voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If NMOS transistors have thicker gates to endure high voltage (2.5V), then voltage endurance is improved, but switching speed deteriorates
Solution Approach 1:
The voltage level shifter is divided into two independent paths: a first path for voltage transitions from 0V to 1.2V, and a second path for voltage transitions from 1.2V to 3.3V. This segmentation allows each path to be optimized independently, with the first path using transistors optimized for low-voltage operation and the second path handling high-voltage transitions, thereby resolving the contradiction between voltage endurance and switching speed.
Solution Approach 2:
A voltage conversion unit is introduced as an intermediary component between the input and output paths. This unit converts the input voltage level before it reaches the second path, allowing the second path to operate at optimized voltage levels without directly承受 the full voltage swing, thus improving switching speed while maintaining voltage endurance.
2Adaptability or versatility
If both PMOS and NMOS transistors are present in the output path, then voltage shifting capability is improved, but output transition speed deteriorates due to transistor competition
Solution Approach 1:
The voltage level shifter is segmented into two separate paths with distinct transistor configurations. The first path uses both PMOS and NMOS transistors for 0V to 1.2V transitions, while the second path is optimized for 1.2V to 3.3V transitions. This segmentation eliminates the competition between PMOS and NMOS transistors in the same path, thereby improving output transition speed while maintaining full voltage shifting capability.
Solution Approach 2:
The circuit dynamically selects different paths based on the input voltage level. When the input voltage is at 0V, the first path is activated; when the input voltage transitions to 1.2V, the second path takes over. This dynamic path selection ensures that only the necessary transistors are active at any given time, reducing competition and improving transition speed.
3Strength
If NMOS transistors have higher threshold voltage for high voltage endurance, then voltage endurance is improved, but switching performance deteriorates
Solution Approach 1:
Different transistor characteristics are applied to different parts of the circuit based on local requirements. The first path uses NMOS transistors with optimized threshold voltages for low-voltage operation, while the second path uses NMOS transistors with higher threshold voltages for high-voltage endurance. This local differentiation allows each part to operate at its optimal performance point without compromising the other.
Solution Approach 2:
The circuit is segmented into two paths that handle different voltage ranges. This segmentation allows the use of transistors with different threshold voltage characteristics in different segments, optimizing both switching performance in the first path and voltage endurance in the second path.
Data Source
AI summary
Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages received by the pull-down circuit are reduced and thus transistors of thinner gates may be used, effectively improving switching speed of transistors in the pull-down circuit. As such, noise and jiggle of the output voltage are reduced.