Voltage Level Shifter Circuit for Parasitic PN Junction Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage level shifters in memory devices face inefficiencies due to parasitic PN junctions and increased chip area, as well as power consumption issues when controlling voltage levels, particularly when the input signal is below the threshold voltage.
Innovation Solution
A voltage level shifter circuit that includes a voltage adjustment circuit, an inverter, and specific transistor configurations to generate an adjustment voltage that adapts to the difference between two input voltages, preventing parasitic PN junctions and optimizing power consumption by using an adjustment voltage that equals either the higher or lower voltage depending on the input conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional high-level shifter architecture is used to shift voltage from VCC to VDD, then voltage level shifting is achieved, but parasitic PN junctions turn on during voltage ramping causing the voltage VDD to fail to increase
Solution Approach 1:
The patent introduces an intermediate control mechanism using the gate terminal of the first transistor to control the timing of parasitic PN junction activation. By applying a control signal to the gate, the invention mediates between the voltage ramping process and the parasitic junction, preventing premature turn-on and ensuring reliable voltage level shifting.
2Reliability
If a fifth transistor is added to prevent parasitic PN junction turn-on, then voltage control reliability is improved, but chip area increases significantly
Solution Approach 1:
The patent makes the existing gate terminal of the first transistor serve multiple functions: it not only controls the primary transistor operation but also acts as a control point for preventing parasitic PN junction turn-on. This multi-functional use of existing components achieves voltage control reliability without requiring additional transistors or increasing chip area.
3Device complexity
If the input signal voltage is below the threshold voltage in a conventional low-level shifter, then the shifter structure is simple, but power consumption increases due to simultaneous turn-on of transistors causing short current
Solution Approach 1:
The patent implements a feedback mechanism where the output signal is fed back to control the gate of the first transistor. This feedback loop monitors the voltage levels and dynamically adjusts the transistor switching timing, preventing simultaneous turn-on of conflicting transistors and eliminating short current paths, thereby reducing power consumption while maintaining simple structure.
Data Source
AI summary
A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a second voltage and for generating an adjustment voltage. When the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.