Voltage Shifter Circuit Timing to Prevent Pull-Up Pull-Down Contention
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Solution Overview
Problem
Voltage shifter circuits face challenges in achieving high speed and wide operation voltage range due to competition between pull-up and pull-down circuits, leading to increased parasitic capacitance, low voltage shifting speed, and difficulty in optimizing duty cycle, especially in 90 nm technology with large voltage differences.
Innovation Solution
A voltage shifter circuit with a control circuit that turns off the pull-up circuit when the input signal changes, avoiding competition between pull-up and pull-down circuits, and utilizing delayers to optimize duty cycle, allowing operation within a wider voltage range with reduced delay time and no direct current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of NMOS transistors NG1 is increased to improve current-driven capacity, then the current-driven capacity is improved, but the parasitic capacitance is increased and the voltage shifting speed is reduced
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the input signal and the pull-up/pull-down circuits. This control circuit generates control signals that coordinate the operation of PMOS and NMOS transistors, preventing simultaneous conduction and eliminating the need to increase transistor size for current driving capability. The intermediary control mechanism resolves the contradiction by enabling adequate current drive without the parasitic capacitance penalty of larger transistors.
Solution Approach 2:
The control circuit performs preliminary action by generating control signals in advance that prepare the pull-up and pull-down circuits for their respective operations. The control signals are generated based on the input signal state, ensuring that the appropriate transistor is activated before voltage transitions occur. This preliminary coordination prevents the need for oversized transistors and maintains fast switching speeds.
2Power
If the size of NMOS transistors NG1 is increased to improve voltage pulling down capacity, then the voltage pulling down capacity is improved, but the parasitic capacitance is increased and the voltage shifting speed is reduced
Solution Approach 1:
The control circuit acts as an intermediary that manages the voltage pulling down operation by selectively activating NMOS transistors only when needed. The control signals ensure that pull-down operations are performed efficiently without requiring permanently large transistor sizes. This intermediary control achieves adequate pulling down capacity while maintaining low parasitic capacitance and high switching speed.
Solution Approach 2:
The patent applies dynamics by making the transistor activation states changeable and adaptive rather than fixed. The control circuit dynamically adjusts which transistors are conducting based on the input signal state, allowing the circuit to achieve high voltage pulling down capacity when needed while maintaining low parasitic capacitance when the transistors are not actively conducting. This dynamic operation resolves the speed-capacity contradiction.
3Adaptability or versatility
If larger area is required due to larger voltage difference in 90 nm technology, then the voltage difference handling capability is improved, but the voltage shifting speed is further affected
Solution Approach 1:
The patent segments the voltage shifting function into multiple controlled stages through the control circuit. Instead of using a single large transistor to handle the full voltage difference, the control circuit divides the operation into coordinated pull-up and pull-down phases with separate transistor pairs. This segmentation allows the circuit to handle large voltage differences (adaptability) while using appropriately sized transistors for each phase, maintaining fast switching speeds.
Solution Approach 2:
The control circuit performs preliminary action by preparing the appropriate transistor configuration before voltage transitions occur. Based on the input signal state, the control circuit pre-configures which transistors will conduct, enabling the circuit to handle large voltage differences efficiently without requiring oversized transistors that would slow down switching. This preliminary preparation maintains speed while achieving voltage difference handling capability.
4Speed
If the competition between pull-up circuit and pull-down circuit is avoided by using control circuit, then the voltage shifting speed is improved, but the device complexity is increased
Solution Approach 1:
The control circuit serves as an intermediary that manages the coordination between pull-up and pull-down circuits, eliminating direct competition while maintaining relatively simple circuit architecture. The control signals generated by the intermediary circuit ensure that only one transistor pair conducts at a time, achieving high voltage shifting speed. The complexity introduced is minimal and centralized in the control logic, making it manageable and efficient.
Data Source
AI summary
The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the competition between the pull-up circuit and the pull-down circuit is avoided. The speed of the voltage shifter circuit is improved and the voltage shifter circuit can operate within a wider voltage range. The delay time of the pull-up circuit and the pull-down circuit is small and the duty cycle is small. In addition, since no direct current path is established, no current is wasted. Additionally, the voltage shifter circuit uses the second delayer to compensate the delay time between the pull-up circuit and the pull-down circuit and optimizes the duty cycle.