Multi-Stage Voltage Level Shifters Within Transistor SOA
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Solution Overview
Problem
Modern integrated circuit (IC) design faces challenges in improving performance, size scaling, and reducing power consumption, as voltage level shifters with low voltage transistors often operate outside the safe operating area (SOA), leading to device stress and early failure, while modifications to avoid this issue increase circuit complexity and power consumption.
Innovation Solution
A voltage level shifter circuit structure connected to multiple voltage rails, using symmetric low-voltage transistors with a maximum voltage rating, operates within the SOA by receiving input voltage pulses between a first positive voltage and ground, and outputs pulses between the first and second positive voltages, minimizing power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If low voltage transistors are used in voltage level shifters, then power consumption is reduced, but the transistors operate outside the safe operating area leading to device stress and early failure
Solution Approach 1:
The voltage level shifter is divided into multiple stages, with each stage handling a portion of the voltage translation. This segmentation allows low voltage transistors to operate within their safe operating area at each stage while achieving the overall voltage translation function, thus maintaining both low power consumption and transistor reliability.
Solution Approach 2:
Intermediate voltage levels are introduced as mediators between the input and output voltage domains. These intermediate levels allow low voltage transistors to operate within their safe operating area by avoiding direct exposure to high voltage stress, thus maintaining reliability while keeping power consumption low.
2Reliability
If asymmetric high voltage transistors (LDMOSFETs) are used to avoid operation outside SOA, then transistor reliability is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The invention uses symmetric low voltage transistors throughout the circuit rather than mixing different transistor types. This homogeneity simplifies the circuit design and reduces complexity while maintaining reliability through proper stage segmentation that keeps all transistors within their safe operating area.
Solution Approach 2:
By segmenting the voltage translation into multiple stages, the circuit can use simple symmetric low voltage transistors in each stage rather than requiring complex asymmetric high voltage transistors, thus reducing overall circuit complexity while maintaining reliability.
3Reliability
If asymmetric high voltage transistors (LDMOSFETs) are used to avoid operation outside SOA, then transistor reliability is improved, but power consumption increases
Solution Approach 1:
Segmenting the voltage translation into multiple stages allows the use of low voltage transistors throughout, which consume less power than high voltage transistors. This maintains transistor reliability while reducing overall power consumption.
Solution Approach 2:
The invention changes the operating parameters by using multiple intermediate voltage levels and configuring transistors to operate within their optimal low voltage range, thereby reducing power consumption while maintaining reliability through proper parameter management at each stage.
Data Source
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AI summary
Disclosed structures include a single-stage (100) and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter (100) and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (IN1, IN1B) (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (OUT1i, OUT1Bi) (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse (OUT1, OUT1B) that transitions between ground and V2) can be output.