Fused Voltage-Shifting Latch for Low-Delay Cross-Domain Signaling
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Solution Overview
Problem
Conventional voltage level shifting circuits and latch circuits in IC devices suffer from higher time delays, limited voltage shifting range, and larger size, making them unsuitable for devices operating in multiple voltage domains, particularly at low voltage levels, which can lead to functionality failures.
Innovation Solution
A fused voltage level shifting circuit that combines the voltage level shifting and latch functions, reducing input-to-output time delay, expanding the voltage shifting range, and minimizing size by using a semiconductor substrate with transistors to operate across different voltage domains, ensuring efficient communication between processing cores and memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional voltage level shifting circuits and latch circuits are used separately, then voltage level shifting and latching functions are achieved, but time delay increases and device size increases
Solution Approach 1:
The patent combines the voltage level shifting circuit and latch circuit into a single integrated unit. The level shifter shares transistors (PMOS and NMOS devices) with the latch circuit, eliminating the need for separate circuits. This merging reduces the total number of components, decreases device area, and reduces propagation delay by removing inter-circuit signal transmission time.
2Adaptability or versatility
If conventional voltage level shifting circuits are used, then voltage level shifting is achieved, but voltage shifting range is limited
Solution Approach 1:
The patent employs dynamic threshold voltage tuning through body biasing to extend the voltage shifting range. By adjusting the threshold voltages of the PMOS and NMOS transistors via body bias control, the circuit can adapt to different voltage domains and maintain reliable operation across a wider voltage range, including low voltage conditions where conventional circuits fail.
Data Source
AI summary
Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.