Voltage-Stacked SRAM Memory Cell Array for Low-Voltage Read/Write
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturization of transistors in SRAMs leads to increased variability in threshold voltages, reducing operation margins and making stable reading and writing at low power supply voltages challenging, especially with high-speed and low leakage current demands.
Innovation Solution
A memory cell array with a top and bottom memory cell array, each with a 6T structure, connected in a voltage-stacked configuration, allowing simultaneous access and symmetric operation, reducing leakage current and maintaining a stable middle voltage for efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are miniaturized to reduce area, then area is reduced, but threshold voltage variability increases and operation margin decreases
Solution Approach 1:
The memory cell is divided into two separate arrays: a top memory cell array and a bottom memory cell array. Each array operates independently with its own bitlines and wordlines, allowing the cell to function as two 6T memory cells rather than one conventional cell. This segmentation enables better control over threshold voltage variations in each segment while maintaining compact area.
Solution Approach 2:
A middle node is introduced as an intermediary between the top and bottom memory cell arrays. This middle node serves as a shared connection point that allows voltage stacking and enables the top and bottom cells to operate independently. The middle node acts as a mediator that facilitates stable voltage levels and reduces the impact of threshold voltage variability in miniaturized transistors.
2Use of energy by stationary object
If power supply voltage is reduced to manage power consumption, then power consumption is reduced, but stable reading and writing becomes challenging
Solution Approach 1:
The memory cell employs dynamic voltage control through the middle node, which can be selectively connected to different voltage levels during read and write operations. The bitlines are dynamically switched between connecting to the middle node or to external bitline drivers, enabling stable operation at reduced power supply voltages by optimizing voltage levels during each operation phase.
Solution Approach 2:
By separating the memory cell into top and bottom arrays with independent bitline connections, each 6T cell can be optimized for low-voltage operation. The segmentation allows one cell to operate while the other is in standby, reducing overall power consumption while maintaining stable read/write operations through selective activation.
3Device complexity
If conventional single array structure is used, then structure is simple, but leakage current is high and area efficiency is low
Solution Approach 1:
The memory cell is segmented into top and bottom 6T memory cell arrays, each with independent bitline connections. This segmentation enables one cell to be in active state while the other is in standby state, significantly reducing leakage current. The dual-array structure allows for better control of threshold voltages and reduced subthreshold leakage compared to conventional single-array designs.
Solution Approach 2:
The patent implements a standby mode where one memory cell array is actively used for storage while the other array is placed in standby with reduced voltage levels. This discarding of one array from active operation during each cycle recovers power that would otherwise be lost as leakage current, while the standby array can quickly transition to active state when needed.
Data Source
AI summary
A memory cell array of an SRAM including: a top memory cell array including top memory cells; and a bottom memory cell array including bottom memory cells, the top memory cells include: a first top memory cell between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the bottom memory cells include: a first bottom memory cell to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when write and read operations are not performed on the first top and bottom memory cells, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are connected to the middle node.