Voltage Supply Circuit Ripple Reduction via Dynamic Clock Frequency
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Solution Overview
Problem
Conventional semiconductor memory voltage supply circuits face challenges in maintaining a stable output voltage due to ripple fluctuations, which affect writing accuracy and data integrity, especially in NAND flash memories where varying cell characteristics and set potentials lead to erroneous writing and reading.
Innovation Solution
A voltage supply circuit that includes a boosting circuit, a voltage detecting circuit, and a control circuit, which adjusts the boosting capability by changing the frequency of the clock signal and the resistance value of a filter circuit to maintain a stable output voltage across multiple set potentials, reducing ripple and improving writing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the boosting circuit operates at high frequency to reduce boosting time, then productivity is improved, but the output voltage exhibits larger ripple fluctuations worsening reliability
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The control circuit dynamically changes the clock frequency based on the set voltage level: using higher frequencies for lower voltages (faster charging) and lower frequencies for higher voltages (reduced ripple). This resolves the contradiction by adapting the frequency to the specific operating conditions.
Solution Approach 2:
The patent changes the clock frequency parameter according to the set voltage. The control circuit selects different clock frequencies from a plurality of available frequencies based on the detected set voltage, thereby optimizing both boosting speed and output stability for different voltage levels.
2Speed
If the clock frequency is increased to speed up the boosting operation, then the boosting capability is improved, but the ripple of the output voltage increases worsening manufacturing precision
Solution Approach 1:
The system dynamically adjusts the clock frequency based on the set voltage level. For lower set voltages, higher frequencies are used to achieve faster charging. For higher set voltages, lower frequencies are used to minimize ripple and ensure writing accuracy. This dynamic adaptation resolves the speed-precision contradiction.
Solution Approach 2:
The clock frequency parameter is changed according to the set voltage detected by the voltage detecting circuit. The control circuit selects appropriate frequency values from a set of available frequencies, optimizing both boosting speed and output voltage stability for different operating conditions.
3Device complexity
If a fixed clock frequency is used for all set voltages, then device complexity is reduced, but the writing characteristics deteriorate due to inability to adapt to varying cell characteristics
Solution Approach 1:
The control circuit is designed to dynamically select clock frequencies based on the set voltage level. This dynamic behavior, while adding some complexity, is implemented through a relatively simple selection mechanism that adapts to different voltage conditions, achieving good writing characteristics without excessive complexity.
Solution Approach 2:
The system changes the clock frequency parameter according to the set voltage detected. The control circuit contains a frequency selection mechanism that chooses appropriate frequencies from a predefined set, providing adaptability to different cell characteristics and voltage levels without requiring a completely complex control system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces ripple fluctuations, ensuring more uniform boosting times and improved data integrity by adapting the boosting capability and filter resistance to match changing set voltages, thereby enhancing the writing and reading performance of semiconductor memory cells.
Implementation Method 1
In the boosting circuit, MOS transistors and capacitances are connected in series and one ends of the capacitance are connected via complementary CLK and CLKB signals to boost the power supply voltage.
Implementation Method 2
a monitor potential outputted from the voltage dividing circuit and a reference potential are compared with each other by the comparator
Implementation Method 3
a filter circuit which has a variable resistor connected between an output of the boosting circuit and the output terminal and filters the voltage outputted from the boosting circuit
Data Source
AI summary
A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit.