Voltage-Switched MRAM Separate Read Write Paths
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Solution Overview
Problem
Conventional MRAM designs face challenges in increasing bit cell density due to the need for large access transistors to ensure sufficient write current, and they suffer from varying read parasitic resistance affecting the tunnel magnetoresistance ratio and sensing margin, especially when using a common electrode for both read and write operations.
Innovation Solution
The implementation of separate read operation circuit paths from a shared spin torque write operation circuit path, where each MRAM bit cell has a dedicated read operation transistor to reduce parasitic resistance and allow for smaller transistor sizing, thereby increasing bit cell density without varying read resistance based on layout and distance from write transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If access transistors are made large to ensure sufficient write current, then write capability is improved, but bit cell density deteriorates
Solution Approach 1:
The patent divides the write current path into two separate paths: one through the access transistor and another through a dedicated write transistor. This segmentation allows the access transistor to be smaller while still achieving sufficient write current through the combined effect of both transistors, thereby resolving the contradiction between write capability and bit cell density.
Solution Approach 2:
The patent introduces a dedicated write transistor as an intermediary component that assists the access transistor in providing sufficient write current. This write transistor acts as a mediator that enables smaller access transistors to achieve the required write current levels, thus improving bit cell density without sacrificing write capability.
2Device complexity
If a common electrode is used for both read and write operations, then device complexity is reduced, but read parasitic resistance varies affecting sensing margin
Solution Approach 1:
The patent segments the electrode functions by providing separate read and write paths. The common electrode is used for write operations, while dedicated read electrodes and read transistors are provided for read operations. This segmentation eliminates the variation in read parasitic resistance that occurs when a common electrode is used for both operations, thereby improving sensing margin while maintaining reasonable device complexity.
3Reliability
If separate read operation transistors are added for each bit cell, then read parasitic resistance is reduced, but device complexity increases
Solution Approach 1:
The patent extracts the read operation function from the common write path by providing dedicated read transistors and read electrodes for each bit cell. This extraction allows read operations to proceed through a separate, optimized path with reduced parasitic resistance, while the common electrode and write transistors continue to handle write operations. The increase in device complexity is justified by the significant improvement in read reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bit cell density by reducing energy requirements for writing and minimizing read parasitic resistance, leading to improved sensing margins and tunnel magnetoresistance ratios, while maintaining efficient data storage and retrieval.
Implementation Method 1
The magnetic orientations of the free and pinned layers can be sensed to read data stored in the MTJ by sensing a resistance when current flows through the MTJ
Implementation Method 2
an MTJ comprises a free ferromagnetic layer ('free layer') disposed above or below a fixed or pinned ferromagnetic layer ('pinned layer')
Implementation Method 3
Recent developments in MTJ devices involve spin-transfer torque (STT)-MTJ devices. In STT-MTJ devices, the spin polarization of carrier electrons, rather than a pulse of a magnetic field, is used to program the state stored in the MTJ
Implementation Method 4
A metal-oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 104 is provided to control reading and writing to the MTJ device 100
Implementation Method 5
The read current Ir is sensed by a sense amplifier 214 coupled to the SL I/O 212 to determine if a logical '0' or logical '1' is stored in the selected MRAM bit cell
Data Source
AI summary
Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.