Voltage Switching Circuit Layout for 3D Memory Row Decoders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional memory devices face challenges in achieving high integration and efficient power usage due to limitations in the arrangement and connectivity of memory cells and voltage switching circuits.
Innovation Solution
A memory device design that includes a first semiconductor layer with a memory cell array and a second semiconductor layer containing a row decoder, page buffer circuit, and a voltage switching circuit, where switching elements are strategically positioned to overlap pass transistors, allowing for efficient voltage transmission and reduced spatial requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If voltage switching circuits are disposed adjacent to memory groups in the first direction, then the memory device structure is simplified, but the resistance change during voltage transmission increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. The voltage switching circuit is moved from an adjacent position in the first direction to a position in a second direction that overlaps the memory group in the first direction. This spatial reconfiguration reduces the transmission path length and minimizes resistance changes while maintaining structural organization.
2Quantity of substance
If memory cells are three-dimensionally stacked to increase integration, then capacity per area increases, but power efficiency and voltage distribution become more challenging
Solution Approach 1:
The memory device is divided into multiple stacked layers with distinct functional regions. The voltage switching circuit is segmented from the memory cell array and positioned in a separate region that overlaps in the first direction. This segmentation allows independent optimization of each region, enabling efficient voltage distribution to the vertically stacked memory cells while maintaining high cell density.
Solution Approach 2:
The patent implements a nested spatial arrangement where the voltage switching circuit in the second direction overlaps and effectively 'contains' the memory group in the first direction. This nested configuration allows the switching circuit to serve multiple memory groups simultaneously, improving power efficiency by reducing redundant voltage transmission paths while maintaining high integration.
3Area of stationary object
If switching elements are positioned to overlap pass transistors, then spatial area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves the manufacturing precision challenge by utilizing the third dimension (vertical stacking). Instead of requiring precise lateral alignment in the same plane, the switching elements are positioned in a second direction that overlaps the pass transistors in the first direction. This vertical separation relaxes lateral alignment tolerances while achieving compact spatial utilization.
Data Source
AI summary
A memory device includes a first semiconductor layer including a memory cell array which is connected to word lines extending in a first direction and bit lines extending in a second direction substantially perpendicular to the first direction; and a second semiconductor layer disposed under the first semiconductor layer, and including a first area overlapping the first semiconductor layer in a third direction substantially perpendicular to the first and second directions and a second area overlapping the first area in the first direction, the second semiconductor layer including a row decoder disposed in the second area, and including pass transistors; and a first voltage switching circuit configured to transmit an operating voltage to the pass transistors, and including switching elements, wherein at least one switching element among the switching elements is disposed in the second area to overlap the pass transistors in the first direction.