Voltage Switching Circuit With Dynamic Well Potential Control
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Solution Overview
Problem
Conventional voltage switching circuits in EEPROMs face challenges in achieving low power consumption while maintaining multiple voltage outputs, as they often require generating a voltage higher than the desired output, leading to increased power consumption and inefficiency.
Innovation Solution
A voltage switching circuit utilizing PMOS transistors with a well potential control section to manage the well voltage of PMOS transistors, allowing for the selection and output of various voltages without reducing the output voltage by the transistor threshold voltage, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage higher than the power supply voltage is generated to compensate for the threshold voltage drop in NMOS switches, then the output voltage can be maintained, but power consumption increases
Solution Approach 1:
The patent changes the operating parameters of the PMOS switches by dynamically adjusting their well potential (substrate voltage) to match the selected output voltage. This parameter change allows the switches to operate without threshold voltage drops affecting the output, eliminating the need to generate higher voltages and thus reducing power consumption while maintaining voltage accuracy.
Solution Approach 2:
The patent implements equipotentiality by connecting the well potential control circuitry that ensures the well potential of each PMOS switch equals the voltage at its source terminal. This creates a potential relationship where Vwell = Vsource, eliminating the threshold voltage drop and allowing direct voltage output without compensation, thereby reducing power consumption while maintaining output accuracy.
2Device complexity
If PMOS switches are used with fixed well potential, then the circuit structure is simple, but the output voltage is reduced by the threshold voltage of the transistor
Solution Approach 1:
The patent applies dynamics by making the well potential of the PMOS switches variable rather than fixed. The well potential control circuitry dynamically adjusts the well potential based on the selected voltage, allowing the circuit to adapt to different output voltage requirements. This dynamic adjustment maintains output voltage accuracy across multiple voltage levels while keeping the overall circuit structure relatively simple.
Solution Approach 2:
The patent changes the well potential parameter of the PMOS switches from a fixed value to a variable value that matches the selected output voltage. This parameter change enables the switches to operate without threshold voltage drops, ensuring accurate voltage output while maintaining circuit simplicity through efficient use of the PMOS transistor characteristics.
3Adaptability or versatility
If multiple voltages are switched using NMOS transistors, then voltage switching functionality is achieved, but the output voltage is always decreased by the threshold voltage of the switch
Solution Approach 1:
The patent changes the well potential parameter of the PMOS switches to match each selected output voltage level. This parameter change allows the switches to maintain the selected voltage accurately without the threshold voltage drop that plagues NMOS-based switching circuits, thereby achieving both voltage switching versatility and output voltage accuracy.
Solution Approach 2:
The patent implements equipotentiality by ensuring that the well potential of each PMOS switch equals the voltage at its source terminal for the selected voltage level. This eliminates the threshold voltage drop effect and allows accurate voltage switching without the output voltage being consistently decreased, achieving both switching functionality and voltage precision.
Data Source
AI summary
A voltage switching circuit selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes a first PMOS transistor that outputs a power supply voltage for operating a logic circuit of an output terminal. A second PMOS transistor outputs a first voltage higher than the power supply voltage to the output terminal. A third PMOS transistor outputs a second voltage lower than the power supply voltage to the output terminal. A well potential control section controls well voltages of the first and third transistors to be the power supply voltage where the power supply voltage and the second voltage are output to the output terminal, and controls the well voltages of the first and third transistors to be the first voltage where the first voltage is output to the output terminal.