Voltage-Based Time-to-Digital Conversion for Low-Power Phase Sampling
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in efficiently capturing time differences between signals and converting them into accurate digital outputs, particularly in high-speed applications where precision and power efficiency are critical.
Innovation Solution
The proposed solution involves a time-to-digital conversion system that utilizes voltage as a representation of time offset. This system includes a time-to-voltage converter circuit that induces a voltage change over a time period between start and stop signals, which is then measured and mapped to a corresponding time value using a voltage measurement circuit and a voltage-to-time mapping circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional delay line based TDCs are used, then time difference measurement is achieved, but power consumption is high and circuit area is large
Solution Approach 1:
The patent replaces the conventional delay line based TDC (which uses multiple delay elements and comparators) with a time-to-voltage converter circuit that converts the time difference between two signals directly into a voltage difference. This substitution of the measurement mechanism reduces power consumption and circuit area while maintaining measurement capability. The time-to-voltage converter uses simpler circuitry (such as current sources and capacitors) compared to the complex delay line structure, thereby achieving lower power consumption and smaller area without sacrificing time measurement functionality.
2Area of stationary object
If conventional delay line based TDCs are used, then time difference measurement is achieved, but circuit area is large
Solution Approach 1:
The patent replaces the conventional delay line based TDC (which uses multiple delay elements and comparators) with a time-to-voltage converter circuit that converts the time difference between two signals directly into a voltage difference. This substitution of the measurement mechanism reduces power consumption and circuit area while maintaining measurement capability. The time-to-voltage converter uses simpler circuitry (such as current sources and capacitors) compared to the complex delay line structure, thereby achieving lower power consumption and smaller area without sacrificing time measurement functionality.
3Object-affected harmful factors
If conventional delay line based TDCs are used, then time difference measurement is achieved, but noise performance is poor
Solution Approach 1:
The patent replaces the conventional delay line based TDC with a time-to-voltage converter that directly converts time difference to voltage difference between two nodes. This substitution eliminates the noise issues inherent in delay line structures (such as jitter from multiple delay stages and comparator noise). The voltage difference can be measured with high precision using standard voltage measurement circuits, achieving superior noise performance and phase offset sampling precision compared to conventional approaches.
4Speed
If high-speed phase offset sampling is achieved with conventional TDCs, then sampling speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action through the use of periodic clock signals to control the time-to-voltage converter and voltage measurement circuit. The converter operates on each clock cycle to capture phase offsets, enabling high-speed sampling without requiring continuous operation of complex delay line structures. This periodic operation allows the circuit to achieve high sampling rates while consuming power only during active measurement intervals, thereby maintaining low overall power consumption despite high-speed operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed phase offset sampling with lower power consumption, smaller circuit area, improved linearity, and better noise performance compared to conventional delay line based TDCs, making it suitable for applications in 5G systems and other high-performance scenarios.
Implementation Method 1
a capacitive circuit (e.g., a capacitor, a capacitor network, or an integrate-and-dump circuit) coupled to the controllable current source and configured to store voltage based on the current output flow from the controllable current source
Implementation Method 2
an integrate-and-dump circuit configured to begin integrating on the start signal and to stop integrating on the stop signal
Implementation Method 3
The voltage measurement circuit may include an analog-to-digital converter to quantize the voltage signal
Data Source
AI summary
A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.