Voltage-Temperature Sensing Circuit for SRAM Read-Margin Control
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Solution Overview
Problem
The increasing leakage current and variations in bitcell leakage due to process variations and temperature in memory devices, particularly in single ended SRAMs, lead to degradation in read 1 margin and false read operations, which existing delay tuning circuits exacerbate by increasing pulse-width and power consumption.
Innovation Solution
A voltage and temperature sensing circuit generates a Pull Down (PD) signal to control primary and secondary pull down paths based on voltage and temperature conditions, adjusting world line pulse width to improve read 1 margin without deteriorating read 0 margin, using secondary pull down paths and temperature/voltage controlled pass gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay tuning circuit is used to improve read operation in memory devices, then read margin is improved in dual sensing memories, but pulse-width and power consumption increase, and read 1 margin deteriorates in single ended memories
Solution Approach 1:
The patent introduces a temperature sensing circuit that detects temperature conditions and dynamically adjusts the pull-down strength parameter. At high temperatures, the circuit strengthens the pull-down action on the dummy bitline to counteract increased leakage current. This parameter adjustment based on temperature conditions improves read 1 margin without requiring continuous increase in pulse-width, thereby avoiding excessive power consumption.
2Productivity
If transistor size is reduced in advanced technology nodes, then device integration is improved, but leakage current increases exponentially
Solution Approach 1:
The patent converts the harmful effect of temperature-induced leakage current into a useful control signal. The temperature sensing circuit detects the temperature condition and uses it to modulate the pull-down strength in the dummy bitline. This transforms the harmful thermal effect into a beneficial control mechanism that automatically compensates for leakage, allowing continued scaling without proportionally increasing leakage power.
3Adaptability or versatility
If process variations increase, then manufacturing flexibility is improved, but bitcell leakage variation increases, causing false read operations
Solution Approach 1:
The patent implements a feedback mechanism where the temperature sensing circuit continuously monitors temperature conditions and feeds this information back to the pull-down control circuit. Based on the sensed temperature, the circuit dynamically adjusts the pull-down strength to compensate for process variations and leakage changes. This closed-loop feedback ensures reliable read operations despite process variations without requiring excessive design margins.
Data Source
AI summary
A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.