Voltage-Tolerant Oscillator Circuit for 3.3V Clock RF Immunity
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Solution Overview
Problem
Pierce gate oscillator circuits in integrated circuits are vulnerable to damage from externally supplied clock signals with peak voltages exceeding the rating of the transistors, particularly in automotive Ethernet applications where the on-chip oscillator operates at 1.8V but may receive a 3.3V clock signal.
Innovation Solution
The design includes a DENMOS transistor positioned between the feedback resistor and the inverter input, ensuring the input voltage to the inverter remains below the 1.8V rating, and incorporates a filter to attenuate noise frequencies, maintaining the common mode voltage at VDD/2 and preventing transistor damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the on-chip oscillator circuit operates at 1.8V but receives a 3.3V externally supplied clock signal, then the oscillator can be driven by higher voltage external clocks, but the transistors may be damaged due to voltage exceeding their rating
Solution Approach 1:
A voltage level shifting circuit is introduced as an intermediary between the external clock input and the on-chip oscillator circuit. This level shifter converts the 3.3V external clock signal to a safe voltage level (1.8V or lower) that the oscillator transistors can tolerate, thereby enabling external clock reception without damaging the internal transistors.
Solution Approach 2:
The design incorporates voltage clamping diodes or protection circuits that activate before voltage damage can occur. These protection elements provide a safety margin by clamping the voltage to safe levels before it can reach the transistor gates, preventing gate oxide breakdown even when 3.3V signals are applied.
2Speed
If transistors are fabricated with a thin gate oxide layer for increased switching speed, then switching speed is improved, but the maximum allowable voltage between terminals is reduced to 1.8V
Solution Approach 1:
The voltage handling function is segmented between different circuit blocks. The input buffer and level-shifting stage handle the higher 3.3V external voltages, while the core oscillator circuit using thin-oxide transistors operates at the lower 1.8V level. This segmentation allows each block to operate within its optimal voltage range without compromising performance.
3Reliability
If the oscillator circuit is designed for 1.8V operation, then transistor reliability is maintained, but the circuit cannot accept 3.3V externally supplied clock signals
Solution Approach 1:
The circuit incorporates voltage level translation capability that dynamically adapts the voltage parameters of incoming signals. The level shifter circuit changes the voltage parameter from 3.3V to 1.8V, and includes detection logic that can identify whether an external clock is present and adjust the operating parameters accordingly, enabling compatibility with both 1.8V and 3.3V external sources.
Data Source
AI summary
An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.