Voltage Tracking Circuit Layout for Compact ESD Protection
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Solution Overview
Problem
The miniaturization of integrated circuits has increased their susceptibility to electrostatic discharge (ESD) due to thinner dielectric thicknesses and lower dielectric breakdown voltages, leading to potential electronic circuit damage.
Innovation Solution
A voltage tracking circuit is implemented using PMOS transistors positioned in separate wells, which enhances ESD immunity and occupies less area by creating a stacked structure that effectively manages ESD events through parasitic diodes and transistors positioned in different wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the dielectric thickness is reduced to enable miniaturization of integrated circuits, then the device size and power consumption are improved, but the susceptibility to electrostatic discharge (ESD) increases due to lower dielectric breakdown voltages
Solution Approach 1:
The circuit is divided into multiple segments with different well configurations. PMOS transistors are positioned in separate wells (first well, second well, third well) to create distinct ESD protection zones. This segmentation allows each region to handle ESD events independently, protecting the overall circuit while maintaining miniaturization benefits.
Solution Approach 2:
Parasitic diodes and transistors positioned in different wells act as intermediaries to divert ESD current away from sensitive circuit elements. These intermediary structures provide alternative current paths that protect the thin dielectric regions from breakdown while allowing the miniaturized device to function normally.
2Reliability
If PMOS transistors are positioned in separate wells to enhance ESD immunity, then ESD protection is improved, but the device area increases
Solution Approach 1:
Multiple functions are merged into the parasitic structures of the PMOS transistors. The same parasitic diodes and transistors that exist as byproducts of the transistor structure are utilized for ESD protection, eliminating the need for separate protection circuits and reducing overall device area.
Solution Approach 2:
The PMOS transistors serve dual purposes: their primary function in the voltage tracking circuit and their secondary function as ESD protection elements through their parasitic structures. This multi-functionality allows ESD immunity to be enhanced without adding dedicated protection components that would increase device area.
3Reliability
If a voltage tracking circuit is implemented to manage ESD events, then ESD protection is improved, but the circuit complexity increases
Solution Approach 1:
The voltage tracking circuit utilizes the inherent parasitic structures of the PMOS transistors for ESD protection without requiring additional control logic or external intervention. The parasitic diodes and transistors automatically activate during ESD events based on voltage conditions, providing self-service protection that simplifies the overall circuit design.
Solution Approach 2:
The circuit leverages changes in voltage parameters to trigger ESD protection mechanisms. When voltage exceeds certain thresholds during ESD events, the parasitic structures automatically change their electrical characteristics to provide protection, eliminating the need for complex control circuits while maintaining reliable ESD management.
Data Source
AI summary
A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.