Voltage-Tracking Timer Circuit for Stable Low-Voltage Delay
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Solution Overview
Problem
Conventional timer circuits face instability and potential shutdown when power supply voltage drops, due to temperature-dependent timer cycles and reliance on constant current sources, making it difficult to operate across a wide range of voltages.
Innovation Solution
A semiconductor circuit design incorporating a current source, capacitor, and comparator, where the current source outputs a voltage-dependent current and reference voltage, and the comparator generates an output signal when the capacitor voltage reaches a predetermined level, maintaining a stable delay time even as the power supply voltage decreases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional timer circuit with temperature-dependent diode characteristic is used, then the timer cycle can be adjusted by temperature, but the circuit stops operating when the power supply voltage drops
Solution Approach 1:
The patent changes the operating parameters by using a current source that outputs current and reference voltage both dependent on the power supply voltage. This allows the circuit to maintain proper operation across a wide range of power supply voltages including lower voltages, resolving the reliability issue while preserving the timer's functional characteristics
2Loss of energy
If the power supply voltage decreases, then energy consumption is reduced, but the timer circuit stops operating
Solution Approach 1:
The patent creates a dynamic system where the current source automatically adjusts its output current and reference voltage in proportion to the power supply voltage. This dynamic adaptation allows the timer circuit to continue operating reliably across varying voltage conditions, maintaining operation continuity while allowing energy consumption to decrease with lower voltages
3Reliability
If a current source outputting current dependent on power supply voltage is used, then the circuit operates stably across wide voltage range, but the circuit complexity increases
Solution Approach 1:
The current source in the patent serves multiple functions simultaneously: it provides the charging current for the capacitor, generates the reference voltage for the comparator, and automatically adapts to varying power supply voltages. This multi-functionality achieves wide voltage range stability while minimizing the increase in circuit complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit ensures stable operation of timer and oscillator circuits across a wide range of power supply voltages by maintaining a consistent delay time, even when the power supply voltage drops, by using a voltage-dependent charging current and reference voltage.
Implementation Method 1
The capacitor is charged with electric charges by the current outputted from the current source
Implementation Method 2
the current source outputs a reference voltage as obtained when the power supply voltage is dropped through a dropping resistance by a predetermined drop voltage
Data Source
AI summary
In a timer circuit of a semiconductor circuit including a current source driven by a power supply voltage, the current source outputs a current dependent on the power supply voltage, and outputs a reference voltage obtained when the power supply voltage is dropped by a predetermined drop voltage. A capacitor is charged with electric charges by the current outputted from the current source. The comparator compares a voltage across the capacitor with the reference voltage from the current source, and outputs an output signal when a voltage across the capacitor is equal to or higher than the reference voltage. The timer circuit outputs an output signal after a delay time, from a timing when supply of the power supply voltage is started, to a timing when the voltage across the capacitor rises substantially in proportion to an elapsed time by charging the capacitor and reaches the reference voltage.


