Operating-Voltage Triggered SCR for Low-Leakage ESD Protection
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Solution Overview
Problem
Semiconductor-controlled rectifiers (SCRs) at advanced technology nodes face limitations due to high leakage and high trigger voltages, which can lead to damage from electrostatic discharge (ESD) before the trigger voltage is reached, compromising the reliability of integrated circuits (ICs).
Innovation Solution
An operating voltage-triggered SCR structure is developed, incorporating a first transistor with two P-type semiconductor terminals, a second transistor with two N-type semiconductor terminals, and optionally an additional transistor, along with PNP and NPN bipolar junction transistors, connected in a trigger control circuitry. This circuitry uses a control signal that switches based on the risk of ESD damage, reducing leakage and triggering SCR operation at a lower voltage and current when necessary, utilizing power-on-reset (POR) to manage the control signal states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode-triggered SCR is used for ESD protection, then the device can provide basic protection functionality, but the trigger voltage is too high which may cause damage before triggering occurs
Solution Approach 1:
The SCR trigger mechanism is segmented into two independent paths: a traditional diode trigger path and a new operating voltage-triggered path using transistors. This segmentation allows the system to choose the appropriate trigger path based on conditions, enabling lower trigger voltage through the transistor-based path while maintaining the original diode-triggered functionality for other cases.
Solution Approach 2:
Transistors are introduced as intermediary components between the operating voltage and the SCR trigger node. These transistors act as controlled switches that can be activated by operating voltage to trigger the SCR at lower voltage levels, mediating the trigger process to avoid direct high-voltage triggering while still providing effective ESD protection.
2Device complexity
If a diode-triggered SCR is used, then the structure is simple, but leakage current is high which increases power consumption
Solution Approach 1:
The transistor-based trigger circuit is configured to activate preliminarily through operating voltage before ESD events occur. By using the normal operating voltage to pre-charge or pre-activate the trigger path, the system reduces the voltage threshold needed for SCR triggering, thereby reducing leakage current during normal operation while maintaining protection capability.
Solution Approach 2:
The trigger characteristics of the SCR are changed by introducing transistor-controlled paths that modify the effective trigger voltage and current parameters. The transistors alter the electrical parameters of the trigger path, enabling the SCR to trigger at lower voltages and reducing leakage current through controlled activation mechanisms.
3Reliability
If the SCR trigger voltage is reduced, then ESD protection effectiveness improves, but leakage current increases which raises power consumption
Solution Approach 1:
The trigger circuit is made dynamic through the use of transistors that can switch between different states based on operating conditions. The transistor-based trigger path dynamically activates when operating voltage is present, providing low-threshold triggering for effective ESD protection, while the switching nature of transistors allows the circuit to minimize leakage current during normal operation by controlling the conduction state.
Data Source
AI summary
A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.